1. Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
- Author
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Hasan Fehmi Ateş, Mohammad Reza Hosseiny Fatemi, Rosli Salleh, Işık Üniversitesi, Mühendislik Fakültesi, Elektrik-Elektronik Mühendisliği Bölümü, Işık University, Faculty of Engineering, Department of Electrical-Electronics Engineering, and Ateş, Hasan Fehmi
- Subjects
Image compression ,Computer science ,Budget control ,Bit-serial architecture ,Reuse ,Pixels ,I/O pins ,Motion estimation ,Subpixel motion estimation ,H.264 standards ,Fast algorithms ,Sum of absolute differences ,Hardware architecture design ,High-speed operation ,Memory access ,Memory requirements ,Hardware architecture ,Macro block ,General Medicine ,Encoder ,Computational complexity ,Video signal processing ,Real time ,Computer engineering ,Hardware and Architecture ,Computational budget ,Operation frequency ,Search method ,Processing speed ,Algorithms ,Reference frame ,Optimization ,Video quality ,Standards ,Design ,Real-time computing ,Macroblock ,Gate count ,Low power application ,Video compression ,Proposed architectures ,Area cost ,H.264 encoders ,Power savings ,High resolution ,Optimization techniques ,Quarter-pixel ,Electrical and Electronic Engineering ,Vlsi architecture ,Sub-pixel motion estimation ,Algorithm level ,Low density ,Power consumption ,Estimation ,H.264 standard - Abstract
This work was supported in part by the Ministry of Higher Education, Malaysia, under Grant FRGS FP094/2007c. We would like to thank the reviewers of this paper for their helpful comments and suggestions which improved our paper. In addition, we would like to thank ARM and Silterra Malaysia for providing the standard cell libraries under the university program and Trans-Dist Engineering for its technical support. The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz. This work was supported in part by the Ministry of Higher Education, Malaysia, under Grant FRGS FP094/2007c. We would like to thank the reviewers of this paper for their helpful comments and suggestions which improved our paper. In addition, we would like to thank ARM and Silterra Malaysia for providing the standard cell libraries under the university program and Trans-Dist Engineering for its technical support Ministry of Education, Malaysia Publisher's version Q4 WOS:000285107500003
- Published
- 2010