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Large-dimensional matrix multiplication is often implemented by submatrix block method. The maximum size of the submatrix determines the speed of the entire matrix multiplication. Concerning the problem that the matrix size directly processed by the classical systolic structure is severely limited by the IO bandwidth, this paper proposes a large-dimensional matrix chain multiplier structure with extremely low IO bandwidth requirements, and completes the hardware design implementation and performance verification. The following is the main work of this thesis. Firstly, optimizing the data organization of matrix multiplication, realizing the input matrix size has nothing to do with IO bandwidth, and make maximum use of the internal logic and storage resources of the device. Secondly, according to the optimized data organization form, the chain multiplier hardware is designed for realizing the source data calculation and transmission overlap operation. Thirdly, the adaptability of the multiplier to the matrix scale is enhanced, and the designed chain multiplier can be configured in real time as multiple independent chains, multiple sets of operations in parallel. Lastly, completing the hardware implementation and performance test of chain multipliers of different sizes on the Xilinx C7V2000T FPGA chip. On this chip, the chain multiplier proposed in this paper supports up to 800 arithmetic units, which is 8 times the size of the classic systolic structure. In the same number of operators, the chain multiplier performance proposed in this paper uses only the classical pulsation structure to calculate the IO bandwidth of 1/8 to obtain equal performance.

A miniaturization research of rocket upper stage electric load management center(EMLC) based on SIP concept is presented in this paper, in the background of electron-integrated system on rocket, focusing on the method of design and implementation of a SIP control system in EMLC. The architecture design of SIP control system is completed with the mixed analog-digital FPGA as hardware platform. A design and implementation method of IPs like main protocol engine core, warm backup fiber optic Ethernet core and other main function core has been elaborated. An assistance health management(AHM) system′s design and implementation method in this paper has been simply illustrated. The simulation result of EMLC and experiment result of the SIP control system are also been given.

In this paper, the design method and application process of a Board Support Package(BSP) based on the Zynq-7000 All Programmable SoC(AP SoC) is implemented. The BSP design is mainly for the field of industrial automated monitoring. It provides an effective implementation process of embedded system BSP, which is beneficial to improve the development efficiency of industrial automated monitoring system. In this paper, In view of the industrial monitoring equipment that uses serial communication mode, the FPGA engineering for small automatic monitoring system is designed, and the embedded Linux system is built by PetaLinux tools, which are designed specifically for FPGA-based SoC. Finally, the correctness and stability of the BSP design are verified with the self-developed hardware platform based on Zynq XC7Z010 series model chip.

In engineering application, when dealing with fuzzy images,due to the way of space deconvolution is more difficult, the frequency domain transformation of the image is usually processed and implemented in the frequency domain.In the light of the frequency domain processing of image deblurring system has such problems as large consumption of hardware resources, poor flexibility of conversion and long processing time, etc. Based on the DE2 development board as the hardware platform, combined with the characteristics of fuzzy image and deblurring algorithm, this paper designs and implements a frequency domain processing method for image deblurring system by means of input data preprocessing, in situ calculation, throwing position, pipeline structure and parallel processing. The experimental data show that the accuracy of the method in the frequency domain processing of the image data is kept above 98%, and the hardware resources only use 9 162 logical units. The experimental results show that the system designed in this paper is superior to other similar systems in processing precision and resource utilization.

Aiming at the problem of low sampling rate and poor portability in the current signal acquisition system, this paper designs a signal acquisition system with high speed and strong portability based on FPGA. Firstly, FPGA samples the signal at a high speed through controlling the ADC. And then，the data is stored in the NAND Flash by using the DMA(Direct Memory Access) mode. Finally, the signal stored in the NAND Flash chip could be demonstrated live by using the LCD. Paper begins with describing the overall design framework of the system. Then, it introduces the hardware design and the implementation, followed by the outcome produced by the experiment that the signal acquisition system samples the ultrasonic signal. The experiment results show that the system could carry on a long-time and multi batch data acquisition stably at relatively high sampling rate.

In order to ensure the real-time performance of the system and solve the problem that the perfect reflection method fails in the exposure environment, this paper proposes an FPGA-based dark channel automatic white balance correction algorithm. According to the light transmittance distribution of the dark channel of the color image, the reference pixels are selected to realize the automatic white balance correction of the color cast pixels. Experimental results show that the dark channel automatic white balance algorithm using FPGA correction can meet the real-time requirements of the entire system and eliminate the environmental impact of overexposure. At the same time, it can be effectively applied to dynamic scenes.

For the test and transmission of rotating parts parameters, a design of a PPM modulation and demodulation system based on FPGA infrared data transmission is proposed, and a CRC check is added in the data transmission process, which increases the accuracy of the data transmission process. This design uses Altera(Intel)′s Cyclone10 series 10CL016YU256C8 chip, which has the characteristics of high speed, high bandwidth, high capacity, etc., suitable for high-speed data communication. Through the Quartus II development platform, it uses Verilog HDL hardware description language to write the corresponding modulation, demodulation and CRC verification programs. The paper introduces the algorithm of 4PPM modulation and demodulation, as well as the algorithm of CRC-CCITT check code, and carries on the timing simulation to the system through Modelsim. The simulation result verifies the correctness of the design.

The implementation of high-performance Viterbi decoding algorithm in resource-constrained processors is a hot topic in recent years. This paper is based on the XC6SLX16-2CSG324 type FPGA processor. In the case of limited resources, in order to balance the problem of Viterbi decoding delay and resource consumption, an improved algorithm is proposed. On the basis of the traditional Viterbi decoding algorithm, the purpose of controlling the path metric value is achieved by maximizing the pre-defined storage path metric value register, and then the stepped survivor path information storage structure is used to complete the storage of the surviving path information and simplifying the decoder hardware implements complexity, reducing decoding delay and resource consumption. Based on the ISE Design Suite 14.7 platform, FPGA-based verification of(2，1，4)-dimensional bit decoders with 20- and 3-bit soft-decision depths is performed, and combined with MATLAB simulation. The results show that the method can effectively reduce the decoding delay and reduce the resource consumption.

Aiming at the long broadcast, much fan in/fan out data path problem brought by high parullelism in the process of the Field Programmable Gate Array(FPGA) to realize the convolution computation in convolutional neural network, this paper adopts pulse array to realize convolution calculation module of convolutional neural network, fixes weights to each processing unit, according to the dimension of the input and output characteristic figure sets to pulse array size, and finally by Vivado high level synthesis realizes convolution calculation module hardware design. The experimental results show that the design has low resource occupancy and good expansibility while realizing the time-series requirements of level 1 pipelining.

In order to meet the real-time and high-precision multi-channel acquisition requirements of a large rotating machinery equipment in the monitoring process, this paper proposes a design scheme of multi-channel vibration signal acquisition and detection system based on FPGA. The system adopts the master/slave FPGA architecture and realizes the 128-channel parallel real-time data acquisition function with a sampling frequency of 100 kHz in the strong noise environment. Then, by designing a random resonance signal detection system with adjustable parameters, the signal-to-noise ratio of the signal is improved and the accuracy of the system detection in the rotating environment is enhanced. The test shows that the system has good real-time performance, stability and effectiveness.

In practical applications, it is difficult to make blurred images clear in spatial domain. Therefore, it is necessary to transform the image in frequency domain and implement image deblurring in frequency domain. When using the development platform of FPGA, image processing is realized by pure hardware, which has strong real-time performance, but consumes too much resources and low execution efficiency. In order to solve this problem, this paper proposes a design scheme of combining hardware and software, which uses DE1-SoC development board as hardware platform, configures Frame Reader, SDRAM, mixer, frequency domain conversion module in FPGA, and maps them to HPS. HPS accesses SDARM using HPS-FPGA bus, and obtains the spectrum of blurred image. In HPS, it uses Linux C programming to estimate the scale and angle for blurred image spectrum, namely PSF, and restores it with classical restoration algorithm to realize blind deblurring. The system uses base 2-DIT-FFT to convert the rows and columns of images in frequency domain. Compared with the inherent IP core and general frequency domain conversion module, the system improves the image quality and reduces the consumption of hardware resources.

This paper analyzes the necessity of verifying the signal integrity of SRAM-based FPGAs, and a method based on simulation for verifying the signal integrity is proposed. Two series of SRAM-based FPGAs, which are Stratix-2 and Virtex-4 respectively, are verified for the signal integrity based on the IBIS model and the HyperLynx software. The results of simulation verification on the valid-data width, voltage amplitude and transmission rate are analyzed. As a result of verifying both FPGAs, the method based on the simulation is feasible for verifying the signal integrity of FPGAs. And also the model parameters are simulated and compared to obtain the difference between the intrinsic mechanism of signal integrity which guides the optimization of device signal integrity.

OLED display device has the characteristics of spontaneous light, short response time, low power consumption, wide color gamut, wide operating temperature range, good seismic resistance and thinness, and has been developed rapidly in the field of small and medium size display.In this paper, the circuit design of the airborne color OLED display module is studied, with a 7.7-inch color OLED display as the display medium and FPGA as the main control chip, which realizes the functions of video display, brightness adjustment and night vision compatibility.

This paper proposed a hardware Trojan detection method based upon XGBoost(eXtreme Gradient Boosting) model by using the analysis results of ring oscillator network, and used the cross-validation method to optimize the model. It can utilize that train sample dataset to build the XGBoost classification model, and use the supervised learn mode to classify the data, thus realizing the separation of the original circuit and the Trojan circuit. Using RS232-T100 and RS232-T800 as Trojan circuits, the FPGA experiment was carried out. The experimental results showed that the detection rate of the Trojan data with RO at 0.1 ms integration time is 100% and 99.20%, which verified the validity of the method. In addition, when compared with traditional methods and other machine learning methods, the XGBoost-based detection method shows a higher detection rate, and can analyze the characteristic importance of the multi-dimensional vector correlation data instead of dimensionality reduction. It can maximize the key features required for Trojan detection.

Traditional way of FPGA configuration file update is using development tools to write FPGA target code to storage devices such as Nor Flash through the JTAG way.However,when the system becomes complicated with multiple FPGA,it takes a long time to update all the FPGA due to the limitation that the JTAG way can only update FPGA once a time. Therefore this paper proposes a FPGA online updating method,which can update multiple FPGA programs at the same time, greatly shorten the update time and reduce the cost of the system.

A FPGA-based data acquisition system is designed，which is operated near space. In order to make the system run stably, this paper designs the system from both hardware and software. On the hardware side, FPGA is used as the controller of the acquisition system due to its strong anti-interference ability. Both the modules of sensor data acquisition and the implementing agency are redundantly processed and divided into main board and slave board to ensure the effectiveness of the system. In terms of software, based on the results of signal classification, it performs modular processing, analyzes the possible problems in the code and designs the state machine to deal with complex tasks. After testing, the data acquisition system can operate stably for a long time, can send sample data in real time, and can also respond to commands from the ground command station.

In recent years, the contribution of polarization code to communication field is becoming more and more prominent, because the theory of polarization code is proved to be able to achieve the channel limit capacity in BDMC. The decoding system of polarization codes can be realized by software or hardware, and the software decoding speed is limited by the CPU serial working mode. So it is of great value for the communication filed to implement the decoder of polarization code on FPGA with parallel working mode. Firstly the SCL decoding algorithm is introduced in this paper. Then the algorithm is optimized to improve the decoding efficiency, and the quantization improvement is carried out on FPGA. Finally, the hardware emulation of the decoder and the performance analysis are carried out on FPGA. The experimental results show that the maximum frequency of the decoder is up to 143.988 MHz, and the throughput is up to 28.79 Mb/s when the code length is 512.

Aiming at the problem that the perimeter of defense zone can’t be located in real time when it is invaded, this paper designed and realized a real-time distributed optical fiber vibration positioning system. The optical path was built on the basis of Mach-Zehnder fiber interference technique，FPGA combined with high speed ADC was used as hardware platform to transform and collect the two signals from the optical path,then the cross correlation was taken as the main algorithm to process the acquired signal to get the vibration position. Tested on a 160-meter fiber, the system can give the vibration position within 500 ms after the vibration occurred. Seting the sampling rate to 10 MHz and after multiple positioning test, the actual positioning error of the system is ±10 m. And the positioning does not need the upper computer, which improves the device portability and reduces the cost.

In order to eliminate the inter symbol interference(ISI) in the communication system and improve the band utilization, the square root-raised cosine filter is often used to realize the base-band shaping filter of the baseband signal. In order to achieve high rate transmission of signals with different symbol rates in communication systems, multi-rate conversion techniques are used in digital signal processing to improve the sampling rate of digital signals. In this paper, SRRC filter and HB, CIC and Farrow filters are cascaded, then a multi-rate converter module based on FPGA is realized. The module can achieve arbitrary multiples of upper sampling , what’s more, by online coefficient reload capability of SRRC filter and online upper insertion ratio reload capability of CIC and Farrow filter, it saves FPGA internal resources effictively. SRRC filter and multi-rate converter module is realized through Verilog programming and the use of IP core on ISE platform. The simulation waveforms of ModelSim and the experimental results are given, raised cosine and multi-rate conversion characteristics are verified, what’s more, the multi-rate conversion module can achieve arbitrary multiples of upper sampling, eliminate the inter symbol interference and improve the band utilization. It is simple to implement effectively.

According to the research status and existing problems of automotive radar, an automotive radar system implementation scheme based on MFSK(multi frequency shift keying) waveform is studied in this paper. The target measurement principle of the system is analyzed in detail, the hardware structure of the system and the implementation process of the FPGA algorithm are introduced too. The algorithm combines all phase FFT and improved CA-CFAR(cell-averaging constant false alarm) algorithm to ensure the measurement accuracy of the system. The experimental results show that the system has high measurement precision, it can achieve the non fuzzy target measurement, and the system runs stably.

In this paper, a deep convolution neural network system is designed and implemented by FPGA hardware platform for the problem that the convolution neural network(CNN) in deep learning is slow and time consuming under the CPU platform. The system uses the rectified linear unit(ReLU) as the characteristic output activation function and uses the Softmax function as the output classifier. Assembly line and the parallelism are used for the feature operation of each layer, so that 295 convolution operations in the entire CNN can be completed in one system clock cycle. The system finally uses the MNIST data set as the experimental, and experimental results show that the training time of FPGA work on 50 MHz is 8.7 times higher than that of general-purpose CPU, and the accuracy rate of system identification after 2 000 iterations is 92.42%.

In view of the complexity and inflexibility of the traditional encoding and decoding algorithms, this paper studies the forward propagation algorithm and structure of autoencoder neural networks. A low power consumption and high speed decoder system is proposed, using the autoencoder neural network as the codec algorithm with FPGA implementation. The system realizes the decoding of characters, and can be applied to the decoding of various multimedia information. Through ModelSim simulation and Xilinx ISE implementation, the hardware measurement are carried out, and the calculation accuracy, resource consumption, calculation speed and power consumption are analyzed. Experimental results show that the designed decoder can decode data correctly, the algorithm is efficient, scalable, the proposed system has the characteristics of low power consumption and high speed, and it can be widely used in a variety of low power, portable products.

The satellite based automatic identification system(AIS) receiver is known to have a narrow signal bandwidth, high Doppler frequency drift and a requirement for low complexity. This paper designs a bandpass sampling AIS noncoherent receiver on FPGA. A two-stage digital down conversion structure is adopted to reduce the FPGA processing pressure and the logic resource consumption. The digital frequency discriminator cascaded by a low pass filter is implemented to achieve non-coherent demodulation of AIS signal. In the AD9246 plus Xilinx xc4vlx80FPGA core board, the AIS signal demodulation is tested to verify our design. The proposed design consumes less resource, and is conducive to the miniaturization of AIS equipment as well as hardware costs reduction.

The integrated industrial control chassis is compatible with all kinds of pluggable boards using CPCI interface. The CPCI design of board card uses special chips to match the FPGA, which reduces the extensibility, and increases the area and cost of the card. In order to solve these problems, a CPCI interface based on FPGA is designed. This paper describes the CPCI protocol implemented with FPGA, simulation and external communication bus protocol, external interrupt mechanism, and conflict avoidance mechanism. This design is used in various CPCI cards produced by the mass production, and it is used in the CPCI chassis of various manufacturers. Compared with the traditional implementation scheme, the scheme has the advantages of low cost, small size, good flexibility and high compatibility. It has obvious advantages in the field of small industrial control.

In a Viterbi decoder, there are two known memory organization techniques for the storage of survivor sequences, namely register exchange method and traceback method. This paper presents a new survivor path storage scheme that enables short latency in area-efficient Viterbi decoder. This is achieved by introducing part register exchange method into traditional traceback method. Since more path information is read per clock,the traceback time is largely shortened, and the path memory size is also saved greatly. On contrast to conventional register exchange and traceback method, the new method has obvious advantage of hign speed,low resource cost and low-latency.

In this paper, an active noise control platform for the vehicle is built based on FPGA. The platform can correctly collect the speed, vibration acceleration and noise of the vehicle in real time, and provide a hardware platform for the related noise reduction algorithm. Compared with the traditional serial processing based acquisition system, the platform can strictly guarantee the time synchronization of multiple signals, and its scalability allows users to easily increase the number of channels according to their own needs, and no additional processor is required. FPGA programmability can guarantee the full verification and design of noise reduction algorithm. The construction of the whole platform provides a strong foundation for the continuous research of active noise reduction.

IRIG-B time code(B code) becomes the suitable standard code for time system equipment because of its superior capacity, simple implementation and easy deployment. IRIG-B code time system is used for time information transfer and time synchronization between different ranges in the shooting range system. However, with the development of large-scale integrated circuit and PLD，and with the enhancement of acquiring of integrability and programmability for timing equipment, conventional time unified system cannot meet the requirement. In order to solve those problems, we put forward a VPX time unified system design based on FPGA, which has the characters of high reliability and integrability, high operability and scalability, and small volume as well. In addition, the design implemented in this paper could support more applications.