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In this paper, we address the problem of improving the performance of real-time embedded Multiprocessor System-on-Chip (MPSoC). Such MPSoCs often execute applications composed of multiple tasks. The tasks on each processor are scheduled by a Real-Time Operating System (RTOS) instance. To improve performance, we reduce the Worst Case Execution Time (WCET) of the RTOS by new processor-coprocessor execution models using reconfigurable hardware. Furthermore, we integrate the proposed contributions on an MPSoC platform, where the processor-coprocessor execution models are applied on three reconfigurable coprocessors - Hardware Task-Status Manager (HWTSM), Thread Interrupt State Controller (TISC), and Remote Slack Manager (RSM). As a case study, we investigate the HWTSM, which determines the execution eligibility of tasks. The experimental results suggest overall system improvement up to 13.3% with the help of the HWTSM. Moreover, the TISC can boost further the performance and RSM can significantly reduce the energy consumption.

In this paper, we address the problem of improving the performance of real-time embedded Multiprocessor System-on-Chip (MPSoC). Such MPSoCs often execute applications composed of multiple tasks. The tasks on each processor are scheduled by a Real-Time Operating System (RTOS) instance. To improve performance, we reduce the Worst Case Execution Time (WCET) of the RTOS by new processor-coprocessor execution models using reconfigurable hardware. Furthermore, we integrate the proposed contributions on an MPSoC platform, where the processor-coprocessor execution models are applied on three reconfigurable coprocessors - Hardware Task-Status Manager (HWTSM), Thread Interrupt State Controller (TISC), and Remote Slack Manager (RSM). As a case study, we investigate the HWTSM, which determines the execution eligibility of tasks. The experimental results suggest overall system improvement up to 13.3% with the help of the HWTSM. Moreover, the TISC can boost further the performance and RSM can significantly reduce the energy consumption.

Increasingly more computing power is being demanded in the domain of multimedia applications. Computer architectures based on reconfigurable hardware are becoming more popular now that classical drawbacks are diminishing. FPGA are constantly improving in terms of performance and area, and provide a technology platform that allows fast and complex reconfigurable designs. The MOLEN polymorphic processor provides the possibility of executing an application-specific core in a custom generated hardware unit, which resides inside a reconfigurable fabric. This thesis presents the architectural design and implementation of a reconfigurable and extensible open source VLIW processor: ?-VEX. In addition to architectural extensibility, our processor also supports reconfigurable operations. Furthermore, we present an application development framework to optimally exploit the freedom of reconfigurable operations. Because ?-VEX is based on the VEX ISA, we already have a good compiler which is able to deal with ISA extensibility and reconfigurable operations. Our processor is targeted to be a CCU within a MOLEN reconfigurable computing machine. To estimate the performance gains, we present a performance analysis based on the VEX simulator. Results of benchmarks on real hardware show that different configurations of our processor in a stand-alone environment lead to considerable cycle count reductions for a selected benchmark application. 1-, 2-, and 4-issue ?-VEX configurations were synthesized and implemented in real hardware to operate at a maximum clock frequency of 89 MHz., Electrical Engineering, Mathematics and Computer Science

Increasingly more computing power is being demanded in the domain of multimedia applications. Computer architectures based on reconfigurable hardware are becoming more popular now that classical drawbacks are diminishing. FPGA are constantly improving in terms of performance and area, and provide a technology platform that allows fast and complex reconfigurable designs. The MOLEN polymorphic processor provides the possibility of executing an application-specific core in a custom generated hardware unit, which resides inside a reconfigurable fabric. This thesis presents the architectural design and implementation of a reconfigurable and extensible open source VLIW processor: ?-VEX. In addition to architectural extensibility, our processor also supports reconfigurable operations. Furthermore, we present an application development framework to optimally exploit the freedom of reconfigurable operations. Because ?-VEX is based on the VEX ISA, we already have a good compiler which is able to deal with ISA extensibility and reconfigurable operations. Our processor is targeted to be a CCU within a MOLEN reconfigurable computing machine. To estimate the performance gains, we present a performance analysis based on the VEX simulator. Results of benchmarks on real hardware show that different configurations of our processor in a stand-alone environment lead to considerable cycle count reductions for a selected benchmark application. 1-, 2-, and 4-issue ?-VEX configurations were synthesized and implemented in real hardware to operate at a maximum clock frequency of 89 MHz., Electrical Engineering, Mathematics and Computer Science

De Blokkers doet denken aan een door mensen gebouwd element met een specifiek doel, omdat het geometrisch van vorm is en door twee parallel lopende vaarten omgeven wordt.