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Body worn wireless sensors for monitoring health information is a promising new application. In developing these sensors, a communication channel model is essential. However, there are currently few measurements or models describing propagation around the body. To address this problem, we have measured electromagnetic waves near the torso and derived relevant statistics. We find that components diffracting around the body are well modeled using correlated log normal variables, and a Nakagami-m distribution can be used to incorporate the influence of arm motions. We have implement this model and evaluated it in terms of important communication metrics. This paper describes body area propagation statistics and proposes a suitable computer model implementation. © 2006 IEEE., special issue on Ultra-Wideband, SCOPUS: cp.j, info:eu-repo/semantics/published

Body worn wireless sensors for monitoring health information is a promising new application. In developing these sensors, a communication channel model is essential. However, there are currently few measurements or models describing propagation around the body. To address this problem, we have measured electromagnetic waves near the torso and derived relevant statistics. We find that components diffracting around the body are well modeled using correlated log normal variables, and a Nakagami-m distribution can be used to incorporate the influence of arm motions. We have implement this model and evaluated it in terms of important communication metrics. This paper describes body area propagation statistics and proposes a suitable computer model implementation. © 2006 IEEE., special issue on Ultra-Wideband, SCOPUS: cp.j, info:eu-repo/semantics/published

State-of-the art electronic systems include ever more features and gather mixed-signal subsystems, possibly from different physical domains. At the same time, cost and development time are reduced; stressing the need for an efficient design flow for fast and reliable design. The present thesis contributes to the construction of an improved design flow supported by mixed-signal hardware description languages (HDL-AMS). In a hierarchical view, the electronic systems are recursively divided into subsystems, down to basic cells and transistor level. The typical design flow results of a top-down synthesis, from the system specifications to the physical realizations, and of a bottom-up validation, from the test of the basic cells up to the test of the system. To improve the link between the technological level and the basic cells, we develop a measurement-based analog ID card which aims to optimize the analog performance and the reliability at high temperature by enabling the choice of optimal process (bulk vs. partially-depleted silicon-on-insulator (SOI) vs. fully-depleted SOI), optimal devices (e.g. multi-threshold voltages process) and optimal bias (weak vs. moderate vs. strong inversion). In the present thesis, we deal with the following analog performance parameters: gain, gain-bandwidth product, MOSFET mismatch in weak inversion and harmonic distortion of MOSFETs in triode regime. We show that SOI transistors are still advantageous over bulk in deep-submicron CMOS technologies and that short-channel SOI transistors can safely be used for mixed-signal operation up to 250°C. The analog ID card can be included in the design flow supported by HDL-AMS. Behavioral models for the basic cells are developed using such languages and further assembled into a ÄÓ modulator with continuous-time integrators as it is a good candidate for low-power consumption and operation at high temperature. The related design issues are assessed using the behavioral models and a design optimiza, (FSA 3)--UCL, 2005

The present work is dedicated to the development of high performance integrated circuits for wireless communications, by acting of three different levels: technologies, devices, and circuits. Silicon-on-Insulator (SOI) CMOS technology is used in the frame of this work. Micromachining technologies are also investigated for the fabrication of three-dimensional tunable capacitors. The reliability of micromachined thin-film devices is improved by the coating of silanes in both liquid- and vapor-phases. Since in telecommunication applications, distortion is responsible for the generation of spurious frequency bands, the linearity behavior of different SOI transistors is analyzed. The validity range of the existing low-frequency nonlinear characterization methods is discussed. New simple techniques valid at both low- and high-frequencies, are provided, based on the integral function method and on the Volterra series. Finally, the design of a crucial nonlinear circuit, the voltage-controlled oscillator, is introduced. The describing function formalism is used to evaluate the oscillation amplitude and is embedded in a design methodology. The frequency tuning by SOI varactors is analyzed in both small- and large-signal regimes., (FSA 3)--UCL, 2004

In recent years, the technique of simplification during generation has turned out to be very promising for the efficient computation of approximate symbolic network functions for large transistor circuits. In this paper it is shown how symbolic network functions can be simplified during their generation with any well-known symbolic network analysis method. The underlying algorithm for the different techniques is always a matroid intersection algorithm. It is shown that the most efficient technique is the two-graph method. An implementation of the simplification during generation technique with the two-graph method illustrates its benefits for the symbolic analysis of large analog circuits.

In recent years, the technique of simplification during generation has turned out to be very promising for the efficient computation of approximate symbolic network functions for large transistor circuits. In this paper it is shown how symbolic network functions can be simplified during their generation with any well-known symbolic network analysis method. The underlying algorithm for the different techniques is always a matroid intersection algorithm. It is shown that the most efficient technique is the two-graph method. An implementation of the simplification during generation technique with the two-graph method illustrates its benefits for the symbolic analysis of large analog circuits.

In recent years, the technique of simplification during generation has turned out to be very promising for the efficient computation of approximate symbolic network functions for large transistor circuits. In this paper it is shown how symbolic network functions can be simplified during their generation with any well-known symbolic network analysis method. The underlying algorithm for the different techniques is always a matroid intersection algorithm. It is shown that the most efficient technique is the two-graph method. An implementation of the simplification during generation technique with the two-graph method illustrates its benefits for the symbolic analysis of large analog circuits.

In recent years, the technique of simplification during generation has turned out to be very promising for the efficient computation of approximate symbolic network functions for large transistor circuits. In this paper it is shown how symbolic network functions can be simplified during their generation with any well-known symbolic network analysis method. The underlying algorithm for the different techniques is always a matroid intersection algorithm. It is shown that the most efficient technique is the two-graph method. An implementation of the simplification during generation technique with the two-graph method illustrates its benefits for the symbolic analysis of large analog circuits.

In recent years, the technique of simplification during generation has turned out to be very promising for the efficient computation of approximate symbolic network functions for large transistor circuits. In this paper it is shown how symbolic network functions can be simplified during their generation with any well-known symbolic network analysis method. The underlying algorithm for the different techniques is always a matroid intersection algorithm. It is shown that the most efficient technique is the two-graph method. An implementation of the simplification during generation technique with the two-graph method illustrates its benefits for the symbolic analysis of large analog circuits.

A symbolic analysis tool is presented that generates simplified symbolic expressions for the small-signal characteristics of large analog integrated circuits. The expressions are approximated while they are computed, so that only those terms are generated which remain in the final expression. This principle causes drastic savings in CPU time and memory, compared with previous symbolic analysis tools. In this way, the maximum size of circuits that can be analyzed, is largely increased. By taking into account a range for the value of a circuit parameter rather than one single number, the generated expressions are also more generally valid. Mismatch handling is explicitly taken into account in the algorithm. The capabilities of the new tool are illustrated with several experimental results

A symbolic analysis tool is presented that generates simplified symbolic expressions for the small-signal characteristics of large analog integrated circuits. The expressions are approximated while they are computed, so that only those terms are generated which remain in the final expression. This principle causes drastic savings in CPU time and memory, compared with previous symbolic analysis tools. In this way, the maximum size of circuits that can be analyzed, is largely increased. By taking into account a range for the value of a circuit parameter rather than one single number, the generated expressions are also more generally valid. Mismatch handling is explicitly taken into account in the algorithm. The capabilities of the new tool are illustrated with several experimental results

A symbolic analysis tool is presented that generates simplified symbolic expressions for the small-signal characteristics of large analog integrated circuits. The expressions are approximated while they are computed, so that only those terms are generated which remain in the final expression. This principle causes drastic savings in CPU time and memory, compared with previous symbolic analysis tools. In this way, the maximum size of circuits that can be analyzed, is largely increased. By taking into account a range for the value of a circuit parameter rather than one single number, the generated expressions are also more generally valid. Mismatch handling is explicitly taken into account in the algorithm. The capabilities of the new tool are illustrated with several experimental results

A symbolic analysis tool is presented that generates simplified symbolic expressions for the small-signal characteristics of large analog integrated circuits. The expressions are approximated while they are computed, so that only those terms are generated which remain in the final expression. This principle causes drastic savings in CPU time and memory, compared with previous symbolic analysis tools. In this way, the maximum size of circuits that can be analyzed, is largely increased. By taking into account a range for the value of a circuit parameter rather than one single number, the generated expressions are also more generally valid. Mismatch handling is explicitly taken into account in the algorithm. The capabilities of the new tool are illustrated with several experimental results

A symbolic analysis tool is presented that generates simplified symbolic expressions for the small-signal characteristics of large analog integrated circuits. The expressions are approximated while they are computed, so that only those terms are generated which remain in the final expression. This principle causes drastic savings in CPU time and memory, compared with previous symbolic analysis tools. In this way, the maximum size of circuits that can be analyzed, is largely increased. By taking into account a range for the value of a circuit parameter rather than one single number, the generated expressions are also more generally valid. Mismatch handling is explicitly taken into account in the algorithm. The capabilities of the new tool are illustrated with several experimental results

An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large analogue circuits. The expressions are approximated while they are computed, so that only the most significant terms are generated which remain in the final expression. This principle leads to dramatic savings in CPU time and memory compared to existing techniques, significantly increasing the maximum size of circuits that can be analysed. By taking into account a range for the value of a circuit parameter rather than one single number the generated symbolic expressions are also generally valid.

A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large analog integrated circuits. The method is based upon the approximation of an expression while it is being computed. The CPU time and memory requirements are reduced drastically with regard to previous approaches, as only those terms are calculated which will remain in the final expression. As a consequence, the maximum circuit size amenable to symbolic analysis has largely increased. The simplification procedure explicitly takes into account variation ranges of the symbolic parameters to avoid inaccuracies of conventional approaches which use a single value. The new approach is also able to take into account mismatches between the symbolic parameters.

An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large analogue circuits. The expressions are approximated while they are computed, so that only the most significant terms are generated which remain in the final expression. This principle leads to dramatic savings in CPU time and memory compared to existing techniques, significantly increasing the maximum size of circuits that can be analysed. By taking into account a range for the value of a circuit parameter rather than one single number the generated symbolic expressions are also generally valid.

A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large analog integrated circuits. The method is based upon the approximation of an expression while it is being computed. The CPU time and memory requirements are reduced drastically with regard to previous approaches, as only those terms are calculated which will remain in the final expression. As a consequence, the maximum circuit size amenable to symbolic analysis has largely increased. The simplification procedure explicitly takes into account variation ranges of the symbolic parameters to avoid inaccuracies of conventional approaches which use a single value. The new approach is also able to take into account mismatches between the symbolic parameters.

An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large analogue circuits. The expressions are approximated while they are computed, so that only the most significant terms are generated which remain in the final expression. This principle leads to dramatic savings in CPU time and memory compared to existing techniques, significantly increasing the maximum size of circuits that can be analysed. By taking into account a range for the value of a circuit parameter rather than one single number the generated symbolic expressions are also generally valid.

A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large analog integrated circuits. The method is based upon the approximation of an expression while it is being computed. The CPU time and memory requirements are reduced drastically with regard to previous approaches, as only those terms are calculated which will remain in the final expression. As a consequence, the maximum circuit size amenable to symbolic analysis has largely increased. The simplification procedure explicitly takes into account variation ranges of the symbolic parameters to avoid inaccuracies of conventional approaches which use a single value. The new approach is also able to take into account mismatches between the symbolic parameters.

A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large analog integrated circuits. The method is based upon the approximation of an expression while it is being computed. The CPU time and memory requirements are reduced drastically with regard to previous approaches, as only those terms are calculated which will remain in the final expression. As a consequence, the maximum circuit size amenable to symbolic analysis has largely increased. The simplification procedure explicitly takes into account variation ranges of the symbolic parameters to avoid inaccuracies of conventional approaches which use a single value. The new approach is also able to take into account mismatches between the symbolic parameters.

An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large analogue circuits. The expressions are approximated while they are computed, so that only the most significant terms are generated which remain in the final expression. This principle leads to dramatic savings in CPU time and memory compared to existing techniques, significantly increasing the maximum size of circuits that can be analysed. By taking into account a range for the value of a circuit parameter rather than one single number the generated symbolic expressions are also generally valid.

An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large analogue circuits. The expressions are approximated while they are computed, so that only the most significant terms are generated which remain in the final expression. This principle leads to dramatic savings in CPU time and memory compared to existing techniques, significantly increasing the maximum size of circuits that can be analysed. By taking into account a range for the value of a circuit parameter rather than one single number the generated symbolic expressions are also generally valid.

A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large analog integrated circuits. The method is based upon the approximation of an expression while it is being computed. The CPU time and memory requirements are reduced drastically with regard to previous approaches, as only those terms are calculated which will remain in the final expression. As a consequence, the maximum circuit size amenable to symbolic analysis has largely increased. The simplification procedure explicitly takes into account variation ranges of the symbolic parameters to avoid inaccuracies of conventional approaches which use a single value. The new approach is also able to take into account mismatches between the symbolic parameters.