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GaAs was central to the development of quantum devices but is rarely used for nanowire-based quantum devices with InAs, InSb and SiGe instead taking the leading role. p-type GaAs nanowires offer a path to studying strongly confined 0D and 1D hole systems with strong spin–orbit effects, motivating our development of nanowire transistors featuring Be-doped p-type GaAs nanowires, AuBe alloy contacts and patterned local gate electrodes towards making nanowire-based quantum hole devices. We report on nanowire transistors with traditional substrate back-gates and EBL-defined metal/oxide top-gates produced using GaAs nanowires with three different Be-doping densities and various AuBe contact processing recipes. We show that contact annealing only brings small improvements for the moderately doped devices under conditions of lower anneal temperature and short anneal time. We only obtain good transistor performance for moderate doping, with conduction freezing out at low temperature for lowly doped nanowires and inability to reach a clear off-state under gating for the highly doped nanowires. Our best devices give on-state conductivity 95 nS, off-state conductivity 2 pS, on-off ratio $\sim {10}^{4}$, and sub-threshold slope 50 mV/dec at $T=4$ K. Lastly, we made a device featuring a moderately doped nanowire with annealed contacts and multiple top-gates. Top-gate sweeps show a plateau in the sub-threshold region that is reproducible in separate cool-downs and indicative of possible conductance quantisation highlighting the potential for future quantum device studies in this material system

The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the subthreshold slope, the threshold voltage and the interface trap density are the key parameters under analysis, which has been performed through experimental results together with simulated data. Oscillations in the transconductance and output conductance have been observed in the experimental results of junctionless devices for temperatures lower than 77 K. The experimental drain current curves also exhibited a 'drain threshold voltage' for the lower temperatures. The impact of the source/drain contact resistance and discrete trap levels has been analyzed by means of simulations.

Nano wires and quantum dots offer new dimensions in semiconductor devices. Potentially superior material quality as well as the large surface to volume ratio and the fact that nature gives you the nano dimensions makes these structures fruitful subjects for research. In particular GaN and AlN and other related compounds offer unique electrical and also optical properties. We have concentrated on the growth of the nano wires, the characterization of their properties, and the demonstration of potentially useful device structures., The original document contains color images.