1. NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS
- Author
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. CRAAX - Centre de Recerca d'Arquitectures Avançades de Xarxes, Pavanello, Fabio, Marchand, Cedric, O’Connor, Ian, Orobtchouk, Regis, Mandorlo, Fabien, Letartre, Xavier, Cueff, Sebastien, Brando Guillaumes, Axel, Cazorla Almeida, Francisco Javier, Canal Corretger, Ramon, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. CRAAX - Centre de Recerca d'Arquitectures Avançades de Xarxes, Pavanello, Fabio, Marchand, Cedric, O’Connor, Ian, Orobtchouk, Regis, Mandorlo, Fabien, Letartre, Xavier, Cueff, Sebastien, Brando Guillaumes, Axel, Cazorla Almeida, Francisco Javier, and Canal Corretger, Ramon
- Abstract
This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases., This project has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No. 101070238., Peer Reviewed, Article signat per 37 autors/es: Fabio Pavanello 1, Cedric Marchand 1, Ian O’Connor 1, Regis Orobtchouk 1, Fabien Mandorlo 1, Xavier Letartre 1, Sebastien Cueff 1, Elena Ioana Vatajelu 2, Giorgio Di Natale 2, Benot Cluzel 3, Aurelien Coillet 3, Benoit Charbonnier 4, Pierre Noe 4, Frantisek Kavan 5, Martin Zoldak 5, Michal Szaj 5, Peter Bienstman 6, Thomas Van Vaerenbergh 7, Ulrich Ruhrmair 8, Paulo Flores 9, Luis Guerra e Silva 9, Ricardo Chaves 9, Luis-Miguel Silveira 9, Mariano Ceccato 10, Dimitris Gizopoulos 11, George Papadimitriou 11, Vasileios Karakostas 11, Axel Brando 12, Francisco J. Cazorla 12, Ramon Canal 12,13, Pau Closas 14, Adria Gusi-Amigo 14, Paolo Crovetti 15, Alessio Carpegna 16, Tzamn Melendez Carmona 16, Stefano Di Carlo 16, Alessandro Savino 16 / 1 Univ. Lyon, Ecole Centrale de Lyon, INSA Lyon, Universite Claude Bernard Lyon 1, CPE Lyon, CNRS, INL; 2 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, 38000 Grenoble, France; 3 ICB UMR CNRS 6303, Universite de Bourgogne Franche-Comte, Dijon, France; 4 Univ. Grenoble Alpes, CEA, LETI, Grenoble, France, 5ARGOTECH, Nachod, Czech Republic; 6 Ghent University - imec, Gent, Belgium; 7 Hewlett Packard Labs, HPE Belgium, B-1831 Diegem, Belgium; 8 Physics Dept. LMU Munchen, Munchen, Germany; 9 INESC-ID Lisboa, Lisbon, Portugal; 10 Department of Computer Science, University of Verona – Verona, Italy; 11 Department of Informatics and Telecommunications, National and Kapodistrian University of Athens, Athens, Greece; 12 Barcelona Supercomputing Center, Barcelona, Spain; 13 Universitat Politecnica de Catalunya, Barcelona, Spain; 14 Albora Technologies SL, Barcelona, Spain; 15 Politecnico di Torino, Dept. of Electronics and Telecommunications (DET), Italy; 16 Politecnico di Torino, Control and Computer Eng. Department, Italy, Postprint (author's final draft)
- Published
- 2023