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An important measure of the development of quantum computing platforms has been the simulation of increasingly complex physical systems. Before fault-tolerant quantum computing, robust error-mitigation strategies were necessary to continue this growth. Here, we validate recently introduced error-mitigation strategies that exploit the expectation that the ideal output of a quantum algorithm would be a pure state. We consider the task of simulating electron systems in the seniority-zero subspace where all electrons are paired with their opposite spin. This affords a computational stepping stone to a fully correlated model. We compare the performance of error mitigations on the basis of doubling quantum resources in time or in space on up to 20 qubits of a superconducting qubit quantum processor. We observe a reduction of error by one to two orders of magnitude below less sophisticated techniques such as postselection. We study how the gain from error mitigation scales with the system size and observe a polynomial suppression of error with increased resources. Extrapolation of our results indicates that substantial hardware improvements will be required for classically intractable variational chemistry simulations.

Quantum many-body systems display rich phase structure in their low-temperature equilibrium states1. However, much of nature is not in thermal equilibrium. Remarkably, it was recently predicted that out-of-equilibrium systems can exhibit novel dynamical phases2-8 that may otherwise be forbidden by equilibrium thermodynamics, a paradigmatic example being the discrete time crystal (DTC)7,9-15. Concretely, dynamical phases can be defined in periodically driven many-body-localized (MBL) systems via the concept of eigenstate order7,16,17. In eigenstate-ordered MBL phases, the entire many-body spectrum exhibits quantum correlations and long-range order, with characteristic signatures in late-time dynamics from all initial states. It is, however, challenging to experimentally distinguish such stable phases from transient phenomena, or from regimes in which the dynamics of a few select states can mask typical behaviour. Here we implement tunable controlled-phase (CPHASE) gates on an array of superconducting qubits to experimentally observe an MBL-DTC and demonstrate its characteristic spatiotemporal response for generic initial states7,9,10. Our work employs a time-reversal protocol to quantify the impact of external decoherence, and leverages quantum typicality to circumvent the exponential cost of densely sampling the eigenspectrum. Furthermore, we locate the phase transition out of the DTC with an experimental finite-size analysis. These results establish a scalable approach to studying non-equilibrium phases of matter on quantum processors.

Systems of correlated particles appear in many fields of modern science and represent some of the most intractable computational problems in nature. The computational challenge in these systems arises when interactions become comparable to other energy scales, which makes the state of each particle depend on all other particles1. The lack of general solutions for the three-body problem and acceptable theory for strongly correlated electrons shows that our understanding of correlated systems fades when the particle number or the interaction strength increases. One of the hallmarks of interacting systems is the formation of multiparticle bound states2-9. Here we develop a high-fidelity parameterizable fSim gate and implement the periodic quantum circuit of the spin-½ XXZ model in a ring of 24 superconducting qubits. We study the propagation of these excitations and observe their bound nature for up to five photons. We devise a phase-sensitive method for constructing the few-body spectrum of the bound states and extract their pseudo-charge by introducing a synthetic flux. By introducing interactions between the ring and additional qubits, we observe an unexpected resilience of the bound states to integrability breaking. This finding goes against the idea that bound states in non-integrable systems are unstable when their energies overlap with the continuum spectrum. Our work provides experimental evidence for bound states of interacting photons and discovers their stability beyond the integrability limit.

Systems of correlated particles appear in many fields of modern science and represent some of the most intractable computational problems in nature. The computational challenge in these systems arises when interactions become comparable to other energy scales, which makes the state of each particle depend on all other particles1. The lack of general solutions for the three-body problem and acceptable theory for strongly correlated electrons shows that our understanding of correlated systems fades when the particle number or the interaction strength increases. One of the hallmarks of interacting systems is the formation of multiparticle bound states2-9. Here we develop a high-fidelity parameterizable fSim gate and implement the periodic quantum circuit of the spin-½ XXZ model in a ring of 24 superconducting qubits. We study the propagation of these excitations and observe their bound nature for up to five photons. We devise a phase-sensitive method for constructing the few-body spectrum of the bound states and extract their pseudo-charge by introducing a synthetic flux. By introducing interactions between the ring and additional qubits, we observe an unexpected resilience of the bound states to integrability breaking. This finding goes against the idea that bound states in non-integrable systems are unstable when their energies overlap with the continuum spectrum. Our work provides experimental evidence for bound states of interacting photons and discovers their stability beyond the integrability limit.

The error rates of quantum devices are orders of magnitude higher than what is needed to run most quantum applications. To close this gap, Quantum Error Correction (QEC) encodes logical qubits and distributes information using several physical qubits. By periodically executing a syndrome extraction circuit on the logical qubits, information about errors (called syndrome) is extracted while running programs. A decoder uses these syndromes to identify and correct errors in real time, which is required to use feedback implemented in quantum algorithms. Unfortunately, software decoders are slow and hardware decoders are fast but less accurate. Thus, almost all QEC studies so far have relied on offline decoding. To enable real-time decoding in near-term QEC, we propose LILLIPUT-- a Lightweight Low Latency Look-Up Table decoder. LILLIPUT consists of two parts-- First, it translates syndromes into error detection events that index into a Look-Up Table (LUT) whose entry provides the error information in real-time. Second, it programs the LUTs with error assignments for all possible error events by running a software decoder offline. LILLIPUT tolerates an error on any operation in the quantum hardware, including gates and measurement, and the number of tolerated errors grows with the size of the code. It needs <7% logic on off-the-shelf FPGAs that allows it to be easily integrated alongside the control and readout circuits in existing systems. LILLIPUT incurs a latency of few nanoseconds and enables real-time decoding. We also propose Compressed LUTs (CLUTs) to reduce the memory needed by LILLIPUT. By exploiting the fact that not all error events are equally likely and only storing data for the most probable error events, CLUTs reduce the memory needed by up-to 107x (from 148 MB to 1.38 MB) without degrading accuracy., Comment: 13 pages,17 Figures, 6 Tables

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Chemistry, 1996., Includes bibliographical references (p. 129-130)., by Venkatesh Locharla Murthy., M.S.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Chemistry, 1996., Includes bibliographical references (p. 129-130)., by Venkatesh Locharla Murthy., M.S.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Chemistry, 1996., Includes bibliographical references (p. 129-130)., by Venkatesh Locharla Murthy., M.S.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Chemistry, 1996., Includes bibliographical references (p. 129-130)., by Venkatesh Locharla Murthy., M.S.

In modern technologies, the DSP algorithms behind the VLSI architectures play a significant role. The latest standards in wireless communications rise the challenges in the implementations of future communications systems. The high-speed Wi-Fi (5G) technology is standardised a few years ago as IEEE 802.11ac standard that adopts an orthogonal frequency division multiplexing (OFDM) technique. The fast Fourier transform (FFT) is a traditional DSP algorithm, that plays a key role in wide range of applications in electrical engineering. In OFDM system, the FFT and inverse fast Fourier transform (IFFT) plays a crucial role. A multiple input multiple output (MIMO) OFDM system needs multiple FFT processors in the receiver and multiple IFFT processors on the transmitter side. The number of FFT/IFFT processors is linearly increased with the number of data streams. For example,an IEEE 802.11ac baseband processor handles up to eight spatial streams. The traditional approach employs eight IFFT processors for the transmitter and eight FFT processors for the receiver. Since the FFT/IFFT processors requirement linearly increases with the number of spatial data streams, implementation of a low power MIMO-OFDM system may not be feasible when the number of spatial streams is more. Hence, it is an interesting research problem to come up with a single FFT/IFFT processor that can handle multiple streams. To this end, there is a scope for developing new algorithms, architectures and design techniques for portable system applications. The objective of this work is to investigate the methodologies and architectures for a variable length multi-path pipelined FFT/IFFT, the input-output data scheduling, reordering and the twiddle coefficient multiplication. Here, the input data scheduling, reordering plays an important role in multiplexing various streams into a single pipeline processor. Output reordering unit aligns the FFT/IFFT output into the standard order. On the other hand, hardware com

In modern technologies, the DSP algorithms behind the VLSI architectures play a significant role. The latest standards in wireless communications rise the challenges in the implementations of future communications systems. The high-speed Wi-Fi (5G) technology is standardised a few years ago as IEEE 802.11ac standard that adopts an orthogonal frequency division multiplexing (OFDM) technique. The fast Fourier transform (FFT) is a traditional DSP algorithm, that plays a key role in wide range of applications in electrical engineering. In OFDM system, the FFT and inverse fast Fourier transform (IFFT) plays a crucial role. A multiple input multiple output (MIMO) OFDM system needs multiple FFT processors in the receiver and multiple IFFT processors on the transmitter side. The number of FFT/IFFT processors is linearly increased with the number of data streams. For example,an IEEE 802.11ac baseband processor handles up to eight spatial streams. The traditional approach employs eight IFFT processors for the transmitter and eight FFT processors for the receiver. Since the FFT/IFFT processors requirement linearly increases with the number of spatial data streams, implementation of a low power MIMO-OFDM system may not be feasible when the number of spatial streams is more. Hence, it is an interesting research problem to come up with a single FFT/IFFT processor that can handle multiple streams. To this end, there is a scope for developing new algorithms, architectures and design techniques for portable system applications. The objective of this work is to investigate the methodologies and architectures for a variable length multi-path pipelined FFT/IFFT, the input-output data scheduling, reordering and the twiddle coefficient multiplication. Here, the input data scheduling, reordering plays an important role in multiplexing various streams into a single pipeline processor. Output reordering unit aligns the FFT/IFFT output into the standard order. On the other hand, hardware com

In modern technologies, the DSP algorithms behind the VLSI architectures play a significant role. The latest standards in wireless communications rise the challenges in the implementations of future communications systems. The high-speed Wi-Fi (5G) technology is standardised a few years ago as IEEE 802.11ac standard that adopts an orthogonal frequency division multiplexing (OFDM) technique. The fast Fourier transform (FFT) is a traditional DSP algorithm, that plays a key role in wide range of applications in electrical engineering. In OFDM system, the FFT and inverse fast Fourier transform (IFFT) plays a crucial role. A multiple input multiple output (MIMO) OFDM system needs multiple FFT processors in the receiver and multiple IFFT processors on the transmitter side. The number of FFT/IFFT processors is linearly increased with the number of data streams. For example,an IEEE 802.11ac baseband processor handles up to eight spatial streams. The traditional approach employs eight IFFT processors for the transmitter and eight FFT processors for the receiver. Since the FFT/IFFT processors requirement linearly increases with the number of spatial data streams, implementation of a low power MIMO-OFDM system may not be feasible when the number of spatial streams is more. Hence, it is an interesting research problem to come up with a single FFT/IFFT processor that can handle multiple streams. To this end, there is a scope for developing new algorithms, architectures and design techniques for portable system applications. The objective of this work is to investigate the methodologies and architectures for a variable length multi-path pipelined FFT/IFFT, the input-output data scheduling, reordering and the twiddle coefficient multiplication. Here, the input data scheduling, reordering plays an important role in multiplexing various streams into a single pipeline processor. Output reordering unit aligns the FFT/IFFT output into the standard order. On the other hand, hardware com