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In many contexts, computers run both critical and untrusted software,necessitating the need for isolating critical software from untrusted software.These computers contain CPUs, memory and peripherals. For performance reasons,some of these peripherals have a direct memory access (DMA) controller (DMAC),allowing them to access memory without involving the CPU. This thesis is a study of memory isolation of peripherals. That is, howperipherals are configured such that they can access only restricted memoryregions. If DMACs are not configured appropriately, they may be able to read andleak sensitive data, or modify and corrupt sensitive data and critical programcode, with potentially disastrous consequences. Since DMACs are configured by anassociated DMAC driver software, the DMAC driver is a critical point for security.Testing drivers for isolation is infeasible, due to the necessity of exhaustivetesting to detect violating writes and differential testing to detect violatingreads. Therefore, we use formal methods and interactive theorem proving (ITP), todevelop formal conditions that, if satisfied by a driver, ensure that theassociated DMAC is memory isolated. We present a detailed case study of formally verifying memory isolation of anEthernet DMAC in the ITP HOL4. We also generalize this case study in the form ofa verification tool in HOL4, reducing the complexity and time needed to formallyverify the conditions under which a DMAC is isolated. The tool includes ageneral DMAC model, reflecting the common features of DMACs. By means ofrefinement, we verified the conditions under which this general DMAC isisolated. By instantiating this general DMAC model with the specifics of a givenDMAC, and by proving the associated proof obligations, the user obtains theformal conditions for DMAC memory isolation. In addition, we have implemented and analyzed a run-time monitor that checksthat Ethernet DMAC configurations respect memory isolation. This monitor is usedin a CCTV syste, Många datorer exekverar både kritisk och opålitlig mjukvara. Detta gör det nödvändig att isolera dessa typer av mjukvara från varandra. Dessa datorer innehåller CPUer, minne och periferienheter. För att maximera prestanda så innehåller vissa periferienheter en minnesstyrkrets för direkt minnesåtkomst som gör att periferienheterna kan läsa och skriva minnet utan inblandning av CPUn. Denna uppsats presenterar en studie av hur periferienheter kan konfigureras så att de är isolerade till vissa minnesregioner. Om minnesstyrkretsen inte är konfigurerad på rätt sätt så kan den möjligtvis läsa och läcka känslig data, eller skriva och förstöra känslig data och kritisk programkod, med förödande konsekvenser. En minnesstyrkrets konfigureras av en tillhörande drivrutin. För att begränsa styrkretsen till vissa minnesregioner så måste därför drivrutinen konfigurera styrkretsen på en motsvarande sätt. Detta gör att drivrutiner för minnesstyrkretsar har en kritisk roll i datorsäkerhet. Testning av drivrutiner för isolering är omöjligt på grund av det stora antalet nödvändiga testfall för att utesluta oönskade minnesåtkomster. Därför använder vi formella metoder och ett interaktivt bevisverktyg för att identifiera formella villkor som garanterar, om satisfierade av drivrutinen, att styrkretsen är minnesisolerad. Vi presenterar en detaljerad formell verifiering i bevisverktyget HOL4 av att en minnesstyrkrets i en Ethernet-adapter är minnesisolerad. Vi generaliserar denna studie i form av ett verifieringsverktyg i HOL4, som reducerar arbetsbördan för att verifiera minnesisolering av minnesstyrkretsar. Verktyget inkluderar en generell model som beskriver de gemensamma operationerna som minnesstyrkretsar utför. Vi har utgått från en abstrakt och generell styrkretsmodell, och steg för steg lagt till mer detaljerade styrkretsoperationer och verifierat att den resulterande modellen respekterar minnesisolering, och slutligen erhållit verifiering av en konkret generell modell som beskriver r, QC 20230523

In many contexts, computers run both critical and untrusted software,necessitating the need for isolating critical software from untrusted software.These computers contain CPUs, memory and peripherals. For performance reasons,some of these peripherals have a direct memory access (DMA) controller (DMAC),allowing them to access memory without involving the CPU. This thesis is a study of memory isolation of peripherals. That is, howperipherals are configured such that they can access only restricted memoryregions. If DMACs are not configured appropriately, they may be able to read andleak sensitive data, or modify and corrupt sensitive data and critical programcode, with potentially disastrous consequences. Since DMACs are configured by anassociated DMAC driver software, the DMAC driver is a critical point for security.Testing drivers for isolation is infeasible, due to the necessity of exhaustivetesting to detect violating writes and differential testing to detect violatingreads. Therefore, we use formal methods and interactive theorem proving (ITP), todevelop formal conditions that, if satisfied by a driver, ensure that theassociated DMAC is memory isolated. We present a detailed case study of formally verifying memory isolation of anEthernet DMAC in the ITP HOL4. We also generalize this case study in the form ofa verification tool in HOL4, reducing the complexity and time needed to formallyverify the conditions under which a DMAC is isolated. The tool includes ageneral DMAC model, reflecting the common features of DMACs. By means ofrefinement, we verified the conditions under which this general DMAC isisolated. By instantiating this general DMAC model with the specifics of a givenDMAC, and by proving the associated proof obligations, the user obtains theformal conditions for DMAC memory isolation. In addition, we have implemented and analyzed a run-time monitor that checksthat Ethernet DMAC configurations respect memory isolation. This monitor is usedin a CCTV syste, Många datorer exekverar både kritisk och opålitlig mjukvara. Detta gör det nödvändig att isolera dessa typer av mjukvara från varandra. Dessa datorer innehåller CPUer, minne och periferienheter. För att maximera prestanda så innehåller vissa periferienheter en minnesstyrkrets för direkt minnesåtkomst som gör att periferienheterna kan läsa och skriva minnet utan inblandning av CPUn. Denna uppsats presenterar en studie av hur periferienheter kan konfigureras så att de är isolerade till vissa minnesregioner. Om minnesstyrkretsen inte är konfigurerad på rätt sätt så kan den möjligtvis läsa och läcka känslig data, eller skriva och förstöra känslig data och kritisk programkod, med förödande konsekvenser. En minnesstyrkrets konfigureras av en tillhörande drivrutin. För att begränsa styrkretsen till vissa minnesregioner så måste därför drivrutinen konfigurera styrkretsen på en motsvarande sätt. Detta gör att drivrutiner för minnesstyrkretsar har en kritisk roll i datorsäkerhet. Testning av drivrutiner för isolering är omöjligt på grund av det stora antalet nödvändiga testfall för att utesluta oönskade minnesåtkomster. Därför använder vi formella metoder och ett interaktivt bevisverktyg för att identifiera formella villkor som garanterar, om satisfierade av drivrutinen, att styrkretsen är minnesisolerad. Vi presenterar en detaljerad formell verifiering i bevisverktyget HOL4 av att en minnesstyrkrets i en Ethernet-adapter är minnesisolerad. Vi generaliserar denna studie i form av ett verifieringsverktyg i HOL4, som reducerar arbetsbördan för att verifiera minnesisolering av minnesstyrkretsar. Verktyget inkluderar en generell model som beskriver de gemensamma operationerna som minnesstyrkretsar utför. Vi har utgått från en abstrakt och generell styrkretsmodell, och steg för steg lagt till mer detaljerade styrkretsoperationer och verifierat att den resulterande modellen respekterar minnesisolering, och slutligen erhållit verifiering av en konkret generell modell som beskriver r, QC 20230523

In many contexts, computers run both critical and untrusted software,necessitating the need for isolating critical software from untrusted software.These computers contain CPUs, memory and peripherals. For performance reasons,some of these peripherals have a direct memory access (DMA) controller (DMAC),allowing them to access memory without involving the CPU. This thesis is a study of memory isolation of peripherals. That is, howperipherals are configured such that they can access only restricted memoryregions. If DMACs are not configured appropriately, they may be able to read andleak sensitive data, or modify and corrupt sensitive data and critical programcode, with potentially disastrous consequences. Since DMACs are configured by anassociated DMAC driver software, the DMAC driver is a critical point for security.Testing drivers for isolation is infeasible, due to the necessity of exhaustivetesting to detect violating writes and differential testing to detect violatingreads. Therefore, we use formal methods and interactive theorem proving (ITP), todevelop formal conditions that, if satisfied by a driver, ensure that theassociated DMAC is memory isolated. We present a detailed case study of formally verifying memory isolation of anEthernet DMAC in the ITP HOL4. We also generalize this case study in the form ofa verification tool in HOL4, reducing the complexity and time needed to formallyverify the conditions under which a DMAC is isolated. The tool includes ageneral DMAC model, reflecting the common features of DMACs. By means ofrefinement, we verified the conditions under which this general DMAC isisolated. By instantiating this general DMAC model with the specifics of a givenDMAC, and by proving the associated proof obligations, the user obtains theformal conditions for DMAC memory isolation. In addition, we have implemented and analyzed a run-time monitor that checksthat Ethernet DMAC configurations respect memory isolation. This monitor is usedin a CCTV syste, Många datorer exekverar både kritisk och opålitlig mjukvara. Detta gör det nödvändig att isolera dessa typer av mjukvara från varandra. Dessa datorer innehåller CPUer, minne och periferienheter. För att maximera prestanda så innehåller vissa periferienheter en minnesstyrkrets för direkt minnesåtkomst som gör att periferienheterna kan läsa och skriva minnet utan inblandning av CPUn. Denna uppsats presenterar en studie av hur periferienheter kan konfigureras så att de är isolerade till vissa minnesregioner. Om minnesstyrkretsen inte är konfigurerad på rätt sätt så kan den möjligtvis läsa och läcka känslig data, eller skriva och förstöra känslig data och kritisk programkod, med förödande konsekvenser. En minnesstyrkrets konfigureras av en tillhörande drivrutin. För att begränsa styrkretsen till vissa minnesregioner så måste därför drivrutinen konfigurera styrkretsen på en motsvarande sätt. Detta gör att drivrutiner för minnesstyrkretsar har en kritisk roll i datorsäkerhet. Testning av drivrutiner för isolering är omöjligt på grund av det stora antalet nödvändiga testfall för att utesluta oönskade minnesåtkomster. Därför använder vi formella metoder och ett interaktivt bevisverktyg för att identifiera formella villkor som garanterar, om satisfierade av drivrutinen, att styrkretsen är minnesisolerad. Vi presenterar en detaljerad formell verifiering i bevisverktyget HOL4 av att en minnesstyrkrets i en Ethernet-adapter är minnesisolerad. Vi generaliserar denna studie i form av ett verifieringsverktyg i HOL4, som reducerar arbetsbördan för att verifiera minnesisolering av minnesstyrkretsar. Verktyget inkluderar en generell model som beskriver de gemensamma operationerna som minnesstyrkretsar utför. Vi har utgått från en abstrakt och generell styrkretsmodell, och steg för steg lagt till mer detaljerade styrkretsoperationer och verifierat att den resulterande modellen respekterar minnesisolering, och slutligen erhållit verifiering av en konkret generell modell som beskriver r, QC 20230523

In many contexts, computers run both critical and untrusted software,necessitating the need for isolating critical software from untrusted software.These computers contain CPUs, memory and peripherals. For performance reasons,some of these peripherals have a direct memory access (DMA) controller (DMAC),allowing them to access memory without involving the CPU. This thesis is a study of memory isolation of peripherals. That is, howperipherals are configured such that they can access only restricted memoryregions. If DMACs are not configured appropriately, they may be able to read andleak sensitive data, or modify and corrupt sensitive data and critical programcode, with potentially disastrous consequences. Since DMACs are configured by anassociated DMAC driver software, the DMAC driver is a critical point for security.Testing drivers for isolation is infeasible, due to the necessity of exhaustivetesting to detect violating writes and differential testing to detect violatingreads. Therefore, we use formal methods and interactive theorem proving (ITP), todevelop formal conditions that, if satisfied by a driver, ensure that theassociated DMAC is memory isolated. We present a detailed case study of formally verifying memory isolation of anEthernet DMAC in the ITP HOL4. We also generalize this case study in the form ofa verification tool in HOL4, reducing the complexity and time needed to formallyverify the conditions under which a DMAC is isolated. The tool includes ageneral DMAC model, reflecting the common features of DMACs. By means ofrefinement, we verified the conditions under which this general DMAC isisolated. By instantiating this general DMAC model with the specifics of a givenDMAC, and by proving the associated proof obligations, the user obtains theformal conditions for DMAC memory isolation. In addition, we have implemented and analyzed a run-time monitor that checksthat Ethernet DMAC configurations respect memory isolation. This monitor is usedin a CCTV syste, Många datorer exekverar både kritisk och opålitlig mjukvara. Detta gör det nödvändig att isolera dessa typer av mjukvara från varandra. Dessa datorer innehåller CPUer, minne och periferienheter. För att maximera prestanda så innehåller vissa periferienheter en minnesstyrkrets för direkt minnesåtkomst som gör att periferienheterna kan läsa och skriva minnet utan inblandning av CPUn. Denna uppsats presenterar en studie av hur periferienheter kan konfigureras så att de är isolerade till vissa minnesregioner. Om minnesstyrkretsen inte är konfigurerad på rätt sätt så kan den möjligtvis läsa och läcka känslig data, eller skriva och förstöra känslig data och kritisk programkod, med förödande konsekvenser. En minnesstyrkrets konfigureras av en tillhörande drivrutin. För att begränsa styrkretsen till vissa minnesregioner så måste därför drivrutinen konfigurera styrkretsen på en motsvarande sätt. Detta gör att drivrutiner för minnesstyrkretsar har en kritisk roll i datorsäkerhet. Testning av drivrutiner för isolering är omöjligt på grund av det stora antalet nödvändiga testfall för att utesluta oönskade minnesåtkomster. Därför använder vi formella metoder och ett interaktivt bevisverktyg för att identifiera formella villkor som garanterar, om satisfierade av drivrutinen, att styrkretsen är minnesisolerad. Vi presenterar en detaljerad formell verifiering i bevisverktyget HOL4 av att en minnesstyrkrets i en Ethernet-adapter är minnesisolerad. Vi generaliserar denna studie i form av ett verifieringsverktyg i HOL4, som reducerar arbetsbördan för att verifiera minnesisolering av minnesstyrkretsar. Verktyget inkluderar en generell model som beskriver de gemensamma operationerna som minnesstyrkretsar utför. Vi har utgått från en abstrakt och generell styrkretsmodell, och steg för steg lagt till mer detaljerade styrkretsoperationer och verifierat att den resulterande modellen respekterar minnesisolering, och slutligen erhållit verifiering av en konkret generell modell som beskriver r, QC 20230523

[ES] En este proyecto se ha diseñado la automatización y los esquemas eléctricos de un fragmento de línea de extracción de medios palés en la que interviene una mesa giratoria para modificar la posición de salida de los palés. Dado al encarecimiento del proyecto que supondría y sus dificultades a la hora de la instalación y mantenimiento al conectar directamente con el autómata debido a su localización, se va a emplear un módulo de E/S remotas el cual comunicara con el PLC mediante el protocolo de comunicaciones TCP/IP. La programación del autómata y la configuración de la isla Advantys STB se realiza en dos softwares diferentes: Unity Pro XL y Advantys. Se debe realizar un programa que rote noventa grados un medio palé respecto el eje vertical, para facilitar su posterior recogida mediante fenwick. Con ello, se pretende mejorar la productividad, optimizar el tiempo empleado y la gestión del almacenamiento, [EN] In this Project the automation and electrical diagrams of a fragment of the extraction line for half pallets have been designed, in which a rotary table intervenes to modify the exit position of the pallets. Given the increased cost of the project and its difficulties at the time of installation and maintenance when connecting directly with the automaton due to its location, a remote I / O module will be used which will communicate with the PLC through the protocol of TCP / IP communications. The programming of the automaton and the configuration of the Advantys STB island is carried out in two different softwares: Unity Pro XL and Advantys. A program must perform a rotaion of half a pallet ninety degrees with respect to the vertical axis to facilitate its subsequent collection by the fenwick. With this, it is intended to improve productivity, optimize time spent and storage management.

[ES] En este proyecto se ha diseñado la automatización y los esquemas eléctricos de un fragmento de línea de extracción de medios palés en la que interviene una mesa giratoria para modificar la posición de salida de los palés. Dado al encarecimiento del proyecto que supondría y sus dificultades a la hora de la instalación y mantenimiento al conectar directamente con el autómata debido a su localización, se va a emplear un módulo de E/S remotas el cual comunicara con el PLC mediante el protocolo de comunicaciones TCP/IP. La programación del autómata y la configuración de la isla Advantys STB se realiza en dos softwares diferentes: Unity Pro XL y Advantys. Se debe realizar un programa que rote noventa grados un medio palé respecto el eje vertical, para facilitar su posterior recogida mediante fenwick. Con ello, se pretende mejorar la productividad, optimizar el tiempo empleado y la gestión del almacenamiento, [EN] In this Project the automation and electrical diagrams of a fragment of the extraction line for half pallets have been designed, in which a rotary table intervenes to modify the exit position of the pallets. Given the increased cost of the project and its difficulties at the time of installation and maintenance when connecting directly with the automaton due to its location, a remote I / O module will be used which will communicate with the PLC through the protocol of TCP / IP communications. The programming of the automaton and the configuration of the Advantys STB island is carried out in two different softwares: Unity Pro XL and Advantys. A program must perform a rotaion of half a pallet ninety degrees with respect to the vertical axis to facilitate its subsequent collection by the fenwick. With this, it is intended to improve productivity, optimize time spent and storage management.

[ES] En este proyecto se ha diseñado la automatización y los esquemas eléctricos de un fragmento de línea de extracción de medios palés en la que interviene una mesa giratoria para modificar la posición de salida de los palés. Dado al encarecimiento del proyecto que supondría y sus dificultades a la hora de la instalación y mantenimiento al conectar directamente con el autómata debido a su localización, se va a emplear un módulo de E/S remotas el cual comunicara con el PLC mediante el protocolo de comunicaciones TCP/IP. La programación del autómata y la configuración de la isla Advantys STB se realiza en dos softwares diferentes: Unity Pro XL y Advantys. Se debe realizar un programa que rote noventa grados un medio palé respecto el eje vertical, para facilitar su posterior recogida mediante fenwick. Con ello, se pretende mejorar la productividad, optimizar el tiempo empleado y la gestión del almacenamiento, [EN] In this Project the automation and electrical diagrams of a fragment of the extraction line for half pallets have been designed, in which a rotary table intervenes to modify the exit position of the pallets. Given the increased cost of the project and its difficulties at the time of installation and maintenance when connecting directly with the automaton due to its location, a remote I / O module will be used which will communicate with the PLC through the protocol of TCP / IP communications. The programming of the automaton and the configuration of the Advantys STB island is carried out in two different softwares: Unity Pro XL and Advantys. A program must perform a rotaion of half a pallet ninety degrees with respect to the vertical axis to facilitate its subsequent collection by the fenwick. With this, it is intended to improve productivity, optimize time spent and storage management.

In this work we present the development of an integrated CMOS analog interface able to convert differential capacitive sensors variations into a DC voltage. The presented circuit is based on autobalancing bridge techniques improving its performances through the linearization of the input/output characteristic and the achievement of the full-range sensor variations capability. Comparison between theoretical and measured interface static behaviour results are reported. © 2020, Springer Nature Switzerland AG.

This master's thesis analyzes the I/O process of IFS. It is presented an easy-to-use development that integrates an asynchronous parallel I/O server called XIOS into IFS. Moreover, different optimization techniques are applied in the integration to minimize the I/O overhead in the IFS execution.

This master's thesis analyzes the I/O process of IFS. It is presented an easy-to-use development that integrates an asynchronous parallel I/O server called XIOS into IFS. Moreover, different optimization techniques are applied in the integration to minimize the I/O overhead in the IFS execution.

Syftet med denna studie är att undersöka hur mycket läraren respektive eleverna använder målspråket i ämnet spanska, steg 1 på gymnasiet, samt undersöka om och i så fall hur lärarens målspråksanvändning påverkar eleverna på en nybörjarnivå i språket. Studien har utförts på två gymnasieskolor med hjälp av observationer och intervjuer av de observerade lärarna samt av elever ur varje klass. Resultaten visar att lärarna använde en väldigt liten del av sin taltid på målspråket, endast 6 %. Eleverna däremot talade mer av sin taltid på målspråket, 54 %. Men det språk som talades på målspråket var ingalunda fritt producerat, utan eleverna använde endast målspråket till att besvara lärarens faktabaserade frågor eller vid styrda kommunikativa övningar. I denna studie fann jag inga direkta kopplingar mellan lärarens och elevernas målspråksanvändning mer än att endast faktabaserat tal på målspråket förekom, från såväl lärare som elever. Även om mina resultat inte visade på några samband mellan lärarens och elevernas målspråksanvändning, står jag fast vid min övertygelse om att ett ökat användande av målspråket från läraren kommer öka elevernas användning av målspråket, vilket även styrks av flertalet språkforskare.

Syftet med denna studie är att undersöka hur mycket läraren respektive eleverna använder målspråket i ämnet spanska, steg 1 på gymnasiet, samt undersöka om och i så fall hur lärarens målspråksanvändning påverkar eleverna på en nybörjarnivå i språket. Studien har utförts på två gymnasieskolor med hjälp av observationer och intervjuer av de observerade lärarna samt av elever ur varje klass. Resultaten visar att lärarna använde en väldigt liten del av sin taltid på målspråket, endast 6 %. Eleverna däremot talade mer av sin taltid på målspråket, 54 %. Men det språk som talades på målspråket var ingalunda fritt producerat, utan eleverna använde endast målspråket till att besvara lärarens faktabaserade frågor eller vid styrda kommunikativa övningar. I denna studie fann jag inga direkta kopplingar mellan lärarens och elevernas målspråksanvändning mer än att endast faktabaserat tal på målspråket förekom, från såväl lärare som elever. Även om mina resultat inte visade på några samband mellan lärarens och elevernas målspråksanvändning, står jag fast vid min övertygelse om att ett ökat användande av målspråket från läraren kommer öka elevernas användning av målspråket, vilket även styrks av flertalet språkforskare.

Almost all existing Networks-on-Chip (NoC) faulttolerant schemes are based on fault-tolerant routing algorithms. In these fault-tolerant schemes, faulty links or routers will be discarded all together. However, only a few part of the discarded link or router is faulty in most cases. It is wasteful to discard the whole link or router. In this paper, we present a slice router architecture which can be used in fine-granularity fault-tolerant NoC. The major motivation of presenting slice router is to refine faulty links and routers. The major idea is that a router is split into several sub-link routers, noted slices. Different from several physically independent routers, slices are coupled together in input/output ports. The coupling of slices makes the network to be able to fine-granularity fault-tolerant. In order to evaluate the fault-tolerant capability of slice routers, we design a looselycoupled 4-slices router with a backup sub-link in each link. Each slice is a single-cycle output buffered switch. Simulation results prove its fault-tolerant capability in the present of high faulty rates. The critical latency is only increased 0.04ns, because the configuration of slice interfaces is parallel with the output arbiter of slices. Under 65nm technology synthesized results show that, the increased area overhead of a slice router is only a few logic gates compared with the non-coupled slice router., QC 20140909

An efficient and flexible air interface is the necessary condition for enabling high data rates next generation wireless systems. A practical answer to this need consists in exploiting channel state information at the transmitter for an adaptive and efficient use of the available radio link resources. This paper contributes with a novel strategy for the allocation of the subcarrier transmit power in the case of a wireless system featuring: i) bit-interleaved coded modulation (BICM); ii) orthogonal frequency division multiplexing (OFDM); iii) multiple antenna profile (MIMO). The proposed power-allocation algorithm aims at maximizing the so-called goodput performance metric for packet transmissions employing automatic repeat request (ARQ) schemes. In addition, it is also proven to be near-optimum in maximizing the input/output mutual information of the MIMO-OFDM subchannels. Numerical simulations over typical wireless indoor scenarios confirm the effectiveness of the procedure when applied in the context of MIMO-BICM-OFDM systems. ©2009 IEEE.

The paper is dedicated to the development of the novel energy saving speed adjustable ac drive with two-stage direct frequency converter (TSDFC) which provides sinusoidal input/output currents and recuperation. Paper describes the two-step control strategy based on the analysis of the TSDFC properties and the problem decomposition. This strategy was realised in the 7.5kW laboratory setup and first in the world 110kW experimental-industrial induction motor drive. The results of experimental study are presented. ©2007 IEEE., IEEE Industrial Electronics Society

Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, . . . ). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I/O scenarios where the periph-erals operate. This software has been used to analyze the performance of four different processors in four I/O scenarios: video capture, video capture and playback, high speed network, and serial transmission.

Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, . . . ). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I/O scenarios where the periph-erals operate. This software has been used to analyze the performance of four different processors in four I/O scenarios: video capture, video capture and playback, high speed network, and serial transmission.

Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, . . . ). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I/O scenarios where the periph-erals operate. This software has been used to analyze the performance of four different processors in four I/O scenarios: video capture, video capture and playback, high speed network, and serial transmission.

Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, . . . ). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I/O scenarios where the periph-erals operate. This software has been used to analyze the performance of four different processors in four I/O scenarios: video capture, video capture and playback, high speed network, and serial transmission.

Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, . . . ). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I/O scenarios where the periph-erals operate. This software has been used to analyze the performance of four different processors in four I/O scenarios: video capture, video capture and playback, high speed network, and serial transmission.

Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, . . . ). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I/O scenarios where the periph-erals operate. This software has been used to analyze the performance of four different processors in four I/O scenarios: video capture, video capture and playback, high speed network, and serial transmission.

The objective of this contribution is to discuss three basic control design methods for disturbance rejection. The key idea is to use a simple fixed continuous time noise model as a design variable to specify the desirable closed loop properties, e.g., the closed loop bandwidth. We will study three closely related controller design methods based on the noise model, namely minimum variance control, weighted minimum variance control and a loop shaping design procedure proposed by Skogestad and Postlethwaite. All these methods lead to simple controller structures, where the transfer function of the input/output relation is the only unknown part. The main motivation of this study has been tuning of controllers for disturbance rejection by means of iterative feedback tuning (IFT). Here, the controller parameters are found by minimizing a specified cost function using gradient search techniques. The gradients are estimated using data from iterative experiments. This is a rather difficult problem if no external input excitation is allowed. Import factors for good results are the controller parametrization and the choice of cost function. We propose an IFT cost function based on a simple output signal weighting tailored to the fixed noise model controller structure. This leads to robust procedure for iterative feedback tuning of a controller for disturbance rejection. The approach is illustrated on a simple example., QC 20120104. Sponsors: 16th Triennial World Congress of International; Federation of Automatic Control, IFAC 2005

The objective of this contribution is to discuss three basic control design methods for disturbance rejection. The key idea is to use a simple fixed continuous time noise model as a design variable to specify the desirable closed loop properties, e.g., the closed loop bandwidth. We will study three closely related controller design methods based on the noise model, namely minimum variance control, weighted minimum variance control and a loop shaping design procedure proposed by Skogestad and Postlethwaite. All these methods lead to simple controller structures, where the transfer function of the input/output relation is the only unknown part. The main motivation of this study has been tuning of controllers for disturbance rejection by means of iterative feedback tuning (IFT). Here, the controller parameters are found by minimizing a specified cost function using gradient search techniques. The gradients are estimated using data from iterative experiments. This is a rather difficult problem if no external input excitation is allowed. Import factors for good results are the controller parametrization and the choice of cost function. We propose an IFT cost function based on a simple output signal weighting tailored to the fixed noise model controller structure. This leads to robust procedure for iterative feedback tuning of a controller for disturbance rejection. The approach is illustrated on a simple example., QC 20120104. Sponsors: 16th Triennial World Congress of International; Federation of Automatic Control, IFAC 2005

The objective of this contribution is to discuss three basic control design methods for disturbance rejection. The key idea is to use a simple fixed continuous time noise model as a design variable to specify the desirable closed loop properties, e.g., the closed loop bandwidth. We will study three closely related controller design methods based on the noise model, namely minimum variance control, weighted minimum variance control and a loop shaping design procedure proposed by Skogestad and Postlethwaite. All these methods lead to simple controller structures, where the transfer function of the input/output relation is the only unknown part. The main motivation of this study has been tuning of controllers for disturbance rejection by means of iterative feedback tuning (IFT). Here, the controller parameters are found by minimizing a specified cost function using gradient search techniques. The gradients are estimated using data from iterative experiments. This is a rather difficult problem if no external input excitation is allowed. Import factors for good results are the controller parametrization and the choice of cost function. We propose an IFT cost function based on a simple output signal weighting tailored to the fixed noise model controller structure. This leads to robust procedure for iterative feedback tuning of a controller for disturbance rejection. The approach is illustrated on a simple example., QC 20120104. Sponsors: 16th Triennial World Congress of International; Federation of Automatic Control, IFAC 2005

The objective of this contribution is to discuss three basic control design methods for disturbance rejection. The key idea is to use a simple fixed continuous time noise model as a design variable to specify the desirable closed loop properties, e.g., the closed loop bandwidth. We will study three closely related controller design methods based on the noise model, namely minimum variance control, weighted minimum variance control and a loop shaping design procedure proposed by Skogestad and Postlethwaite. All these methods lead to simple controller structures, where the transfer function of the input/output relation is the only unknown part. The main motivation of this study has been tuning of controllers for disturbance rejection by means of iterative feedback tuning (IFT). Here, the controller parameters are found by minimizing a specified cost function using gradient search techniques. The gradients are estimated using data from iterative experiments. This is a rather difficult problem if no external input excitation is allowed. Import factors for good results are the controller parametrization and the choice of cost function. We propose an IFT cost function based on a simple output signal weighting tailored to the fixed noise model controller structure. This leads to robust procedure for iterative feedback tuning of a controller for disturbance rejection. The approach is illustrated on a simple example., QC 20120104. Sponsors: 16th Triennial World Congress of International; Federation of Automatic Control, IFAC 2005

The objective of this contribution is to discuss three basic control design methods for disturbance rejection. The key idea is to use a simple fixed continuous time noise model as a design variable to specify the desirable closed loop properties, e.g., the closed loop bandwidth. We will study three closely related controller design methods based on the noise model, namely minimum variance control, weighted minimum variance control and a loop shaping design procedure proposed by Skogestad and Postlethwaite. All these methods lead to simple controller structures, where the transfer function of the input/output relation is the only unknown part. The main motivation of this study has been tuning of controllers for disturbance rejection by means of iterative feedback tuning (IFT). Here, the controller parameters are found by minimizing a specified cost function using gradient search techniques. The gradients are estimated using data from iterative experiments. This is a rather difficult problem if no external input excitation is allowed. Import factors for good results are the controller parametrization and the choice of cost function. We propose an IFT cost function based on a simple output signal weighting tailored to the fixed noise model controller structure. This leads to robust procedure for iterative feedback tuning of a controller for disturbance rejection. The approach is illustrated on a simple example., QC 20120104. Sponsors: 16th Triennial World Congress of International; Federation of Automatic Control, IFAC 2005

The full capacity of contemporary parallel computers can, in the context of iterative ab initio procedures like, for example, self-consistent field (SCF) and multiconfigurational SCF, only be utilized if the disk and input/output (I/O) capacity are fully exploited before the implementation turns to an integral direct strategy. In a recent report on parallel semidirect SCF http://www.tc.cornell.edu/er/media/1996/collabrate.html, http://www.fp.mcs.anl.gd/grand-challenges/chem/non-direct/index.html it was demonstrated that super-linear speedups are achievable for algorithms that exploit scalable parallel I/O. In the I/O-intensive SCF iterations of this implementation a static load balancing, however, was employed, dictated by the initial iteration in which integral evaluation dominates the central processing unit activity and thus determines the load balancing. In the present paper we present the first implementation in which load balancing is achieved throughout the whole SCF procedure, i.e. also in subsequent iterations. The improved scalability of our new algorithm is demonstrated in some test calculations, for example, for 63-node calculation a speedup of 104 was observed in the computation of the two-electron integral contribution to the Fock matrix.

Emphasizes the relationship among technology, hardware organization, and programming systems in the evolution of computer architecture. Pipelined, out-of-order, and speculative execution. Superscaler, VLIW, vector, and multithreaded processors. Addressing structures and virtual memory, and exception handling. I/O and memory systems. Parallel computers; message passing and shared memory systems. Memory models, synchronization, and cache coherence protocols. Vector supercomputers. Assumes an undergraduate knowledge of computer systems. From the course home page: Course Description 6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers.

Emphasizes the relationship among technology, hardware organization, and programming systems in the evolution of computer architecture. Pipelined, out-of-order, and speculative execution. Superscaler, VLIW, vector, and multithreaded processors. Addressing structures and virtual memory, and exception handling. I/O and memory systems. Parallel computers; message passing and shared memory systems. Memory models, synchronization, and cache coherence protocols. Vector supercomputers. Assumes an undergraduate knowledge of computer systems. From the course home page: Course Description 6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers.

The area of parallel and distributed computing has grown very fast in the past few decades with the aim of offering vast computational capabilities that applications can tap into. Applications from the various areas of science and engineering can perform large-scale, high-accuracy computations and simulations with the advent of new machines and architectures. Run-time libraries, operating systems software, performance analysis tools, support for compilers and data base systems are aimed at increasing the productivity and usability of these machines in the hands of applications programmers. Efficient application design and performance analysis and the fine tuning of applications have become an absolute necessity. In this thesis we focus on applications that are highly data intensive and require large amounts of storage and extensive data processing capabilities. As the I/O devices have very high latencies, such applications use many useful processor cycles waiting for disk accesses to complete. This problem is exacerbated in parallel machines since there are many processors with the result that there are multiple high-volume requests to the I/O subsystem, making I/O a troublesome bottleneck. Because of this problem parallel machines require both systems support and the fine tuning of application to achieve efficient implementations. We optimize the I/O activity of some large production applications as well as some small scientific applications and synthetic workloads, and we evaluate and analyze the performance of optimizations on these applications using I/O performance tools. Some of the applications that we study spend around 60% of their execution time performing I/O operations. Optimizations such as prefetching, caching/buffering, collective I/O influence the I/O performance of these applications. In addition, systems attributes such as the number of processors and I/O nodes, the stripe unit and the stripe factor affect the performance. We study the relative imp