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An on-chip compensated wide output range boost converter with fixed-frequency adaptive off-time current-mode control is presented. The small signal characteristic of the boost converter with current-mode control is reviewed, and an adaptive current sensing technique is proposed to reduce the variation of phase margin at different output voltages. On-chip compensation is achieved with a Type II compensator. Adaptive off-time control is adopted for its fast response and no need for slope compensation, while its disadvantage of varying switching frequency is eliminated by the proposed off-time generator. The IC controller was fabricated in a 0.5 mu m 2P3M BCD 40 V process. Measurement results confirm that an output range of 5.5 V similar to 36 V with an input voltage of 5 V is achieved. The switching frequency is fixed at 1 MHz with a variation of +/-1%. The measured peak efficiency and maximum output power are 92.9% and 8.6 W, respectively. For a load step of 200 mA using a 3.3-mu H inductor and a 20-mu F output capacitor, overshoot and undershoot of the load transient responses are smaller than 1% of the output voltage.

A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of -90/-84 dBc/Hz at 100-kHz offset and -94/-88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of 0.39 mm. Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 degrees range with an average resolution of 3.9 and amplitude variation less than +/- 0.1 dB, which makes it suitable for phased-array transceivers.

A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of -90/-84 dBc/Hz at 100-kHz offset and -94/-88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of 0.39 mm. Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 degrees range with an average resolution of 3.9 and amplitude variation less than +/- 0.1 dB, which makes it suitable for phased-array transceivers.

An on-chip compensated wide output range boost converter with fixed-frequency adaptive off-time current-mode control is presented. The small signal characteristic of the boost converter with current-mode control is reviewed, and an adaptive current sensing technique is proposed to reduce the variation of phase margin at different output voltages. On-chip compensation is achieved with a Type II compensator. Adaptive off-time control is adopted for its fast response and no need for slope compensation, while its disadvantage of varying switching frequency is eliminated by the proposed off-time generator. The IC controller was fabricated in a 0.5 mu m 2P3M BCD 40 V process. Measurement results confirm that an output range of 5.5 V similar to 36 V with an input voltage of 5 V is achieved. The switching frequency is fixed at 1 MHz with a variation of +/-1%. The measured peak efficiency and maximum output power are 92.9% and 8.6 W, respectively. For a load step of 200 mA using a 3.3-mu H inductor and a 20-mu F output capacitor, overshoot and undershoot of the load transient responses are smaller than 1% of the output voltage.

A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of -90/-84 dBc/Hz at 100-kHz offset and -94/-88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of 0.39 mm. Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 degrees range with an average resolution of 3.9 and amplitude variation less than +/- 0.1 dB, which makes it suitable for phased-array transceivers.

An on-chip compensated wide output range boost converter with fixed-frequency adaptive off-time current-mode control is presented. The small signal characteristic of the boost converter with current-mode control is reviewed, and an adaptive current sensing technique is proposed to reduce the variation of phase margin at different output voltages. On-chip compensation is achieved with a Type II compensator. Adaptive off-time control is adopted for its fast response and no need for slope compensation, while its disadvantage of varying switching frequency is eliminated by the proposed off-time generator. The IC controller was fabricated in a 0.5 mu m 2P3M BCD 40 V process. Measurement results confirm that an output range of 5.5 V similar to 36 V with an input voltage of 5 V is achieved. The switching frequency is fixed at 1 MHz with a variation of +/-1%. The measured peak efficiency and maximum output power are 92.9% and 8.6 W, respectively. For a load step of 200 mA using a 3.3-mu H inductor and a 20-mu F output capacitor, overshoot and undershoot of the load transient responses are smaller than 1% of the output voltage.

A low-voltage and low-power 96.8-108.5GHz transformer-based PLL is implemented in a 65nm CMOS technology. Consuming only 14.1mW from 0.6V/1.2V supply, the PLL measures phase noise of -84dBc/Hz at 100-kHz offset and -88dBc/Hz at 1-MHz offset from a 99.4GHz carrier while occupying a core chip area of 0.39mm2. Moreover, with an embedded phase shifter, the PLL output phase can be shifted by 360° range with an average resolution of 3.9° and amplitude variation less than ±0.1dB. © 2014 IEEE.

A 2x-oversampling 25Gbps clock and data recovery (CDR) circuit is proposed that employs a charge-based, zero-crossing linearizing phase detector (ZCL-PD). This technique linearizes the conventional bang-bang CDR system, resulting in low quantization jitter, improved loop bandwidth, and improved input sensitivity. To minimize the power consumption, an injection-locked inverter-based 1: 2 divider reduces CML clocking power while maintaining low jitter. The 65nm-CMOS test-chip measurements demonstrate error-free operation for PRBS-7 and PRBS-31, an 120mV differential input sensitivity, a 9MHz jitter transfer bandwidth, 1.08ps/9.63ps (rms/pk-pk) of recovered clock jitter, and 65mW of power consumption.

A 2x-oversampling 25Gbps clock and data recovery (CDR) circuit is proposed that employs a charge-based, zero-crossing linearizing phase detector (ZCL-PD). This technique linearizes the conventional bang-bang CDR system, resulting in low quantization jitter, improved loop bandwidth, and improved input sensitivity. To minimize the power consumption, an injection-locked inverter-based 1: 2 divider reduces CML clocking power while maintaining low jitter. The 65nm-CMOS test-chip measurements demonstrate error-free operation for PRBS-7 and PRBS-31, an 120mV differential input sensitivity, a 9MHz jitter transfer bandwidth, 1.08ps/9.63ps (rms/pk-pk) of recovered clock jitter, and 65mW of power consumption.

A low-voltage and low-power 96.8-108.5GHz transformer-based PLL is implemented in a 65nm CMOS technology. Consuming only 14.1mW from 0.6V/1.2V supply, the PLL measures phase noise of -84dBc/Hz at 100-kHz offset and -88dBc/Hz at 1-MHz offset from a 99.4GHz carrier while occupying a core chip area of 0.39mm2. Moreover, with an embedded phase shifter, the PLL output phase can be shifted by 360° range with an average resolution of 3.9° and amplitude variation less than ±0.1dB. © 2014 IEEE.

A low-voltage and low-power 96.8-108.5GHz transformer-based PLL is implemented in a 65nm CMOS technology. Consuming only 14.1mW from 0.6V/1.2V supply, the PLL measures phase noise of -84dBc/Hz at 100-kHz offset and -88dBc/Hz at 1-MHz offset from a 99.4GHz carrier while occupying a core chip area of 0.39mm2. Moreover, with an embedded phase shifter, the PLL output phase can be shifted by 360° range with an average resolution of 3.9° and amplitude variation less than ±0.1dB. © 2014 IEEE.

A 2x-oversampling 25Gbps clock and data recovery (CDR) circuit is proposed that employs a charge-based, zero-crossing linearizing phase detector (ZCL-PD). This technique linearizes the conventional bang-bang CDR system, resulting in low quantization jitter, improved loop bandwidth, and improved input sensitivity. To minimize the power consumption, an injection-locked inverter-based 1: 2 divider reduces CML clocking power while maintaining low jitter. The 65nm-CMOS test-chip measurements demonstrate error-free operation for PRBS-7 and PRBS-31, an 120mV differential input sensitivity, a 9MHz jitter transfer bandwidth, 1.08ps/9.63ps (rms/pk-pk) of recovered clock jitter, and 65mW of power consumption.

A 1.2 V 12bit programmable pipelined ADC is presented and implemented in 0.13 mu m CMOS technology. A common-mode-sensing-and-input-interchanged OTA-sharing technique is proposed to address the non-resetting and successive-stage crosstalk issues in conventional OTA-sharing technique. Speed options of 5-45 MS/s are available with scalable power obtained by adjusting the bias currents for OTAs, comparators, and reference buffers, etc., or the global bias current. The measured signal-to-distortion-and-noise ratio is in range of 62.5-69.2 dB, and the peak spurious free dynamic range is 80.7 dB for all speed options, while the figure-of-merit is in the range of 0.26-0.49 pJ/conversion. The core area is 1.5 mm(2)., QC 20120703

A wirelessly-powered, near-threshold, body area network SoC supporting synchronized multi-node TDMA operation is demonstrated in 65nm CMOS. A global clock source sent from a base-station wirelessly broadcasts at 434.16MHz to all sensor nodes, where each individual BAN sensor is phase-locked to the base-station clock using a super-harmonic injection-locked frequency divider. Each near-threshold SoC harvests energy from and phase locks to this broadcasted 434.16MHz waveform, eliminating the need for a battery. A Near-V-T MICS-band OOK transmitter sends the synchronized local sensor data back to the base-station in its pre-defined TDMA slot. For an energy-harvested local V-DD=0.56V, measurements demonstrate full functionality over 1.4m between the base-station and four worn sensors, including two that are NLOS. The sensitivity of the RF energy harvesting and the wireless clock synchronization are measured at -8dBm and -35dBm, respectively. ECG Lead-II / Lead-III waveforms are experimentally captured, demonstrating the end-to-end system application.

A 4-element 60-GHz phased-array receiver employs transformer-based hybrid-mode mixing featuring high linearity and high gain. Closed-loop beam-forming calibration is achieved by sequentially performing gain equalization, I/Q calibration, and successive-approximation phase tuning. Implemented in 65nm CMOS, each element measures NF of 6.5dB, gain of 20dB and IP1dB of -12.5dBm. With the proposed beam-forming calibration, the peak-to-null ratio of the array pattern is improved from 16.5.dB to 28.5dB, corresponding to phase error of ±0.6°and amplitude mismatch of ±1.1dB. © 2013 JSAP.

A 4-element 60-GHz phased-array receiver employs transformer-based hybrid-mode mixing featuring high linearity and high gain. Closed-loop beam-forming calibration is achieved by sequentially performing gain equalization, I/Q calibration, and successive-approximation phase tuning. Implemented in 65nm CMOS, each element measures NF of 6.5dB, gain of 20dB and IP1dB of -12.5dBm. With the proposed beam-forming calibration, the peak-to-null ratio of the array pattern is improved from 16.5.dB to 28.5dB, corresponding to phase error of ±0.6°and amplitude mismatch of ±1.1dB. © 2013 JSAP.

A wirelessly-powered, near-threshold, body area network SoC supporting synchronized multi-node TDMA operation is demonstrated in 65nm CMOS. A global clock source sent from a base-station wirelessly broadcasts at 434.16MHz to all sensor nodes, where each individual BAN sensor is phase-locked to the base-station clock using a super-harmonic injection-locked frequency divider. Each near-threshold SoC harvests energy from and phase locks to this broadcasted 434.16MHz waveform, eliminating the need for a battery. A Near-V-T MICS-band OOK transmitter sends the synchronized local sensor data back to the base-station in its pre-defined TDMA slot. For an energy-harvested local V-DD=0.56V, measurements demonstrate full functionality over 1.4m between the base-station and four worn sensors, including two that are NLOS. The sensitivity of the RF energy harvesting and the wireless clock synchronization are measured at -8dBm and -35dBm, respectively. ECG Lead-II / Lead-III waveforms are experimentally captured, demonstrating the end-to-end system application.

A 4-element 60-GHz phased-array receiver employs transformer-based hybrid-mode mixing featuring high linearity and high gain. Closed-loop beam-forming calibration is achieved by sequentially performing gain equalization, I/Q calibration, and successive-approximation phase tuning. Implemented in 65nm CMOS, each element measures NF of 6.5dB, gain of 20dB and IP1dB of -12.5dBm. With the proposed beam-forming calibration, the peak-to-null ratio of the array pattern is improved from 16.5.dB to 28.5dB, corresponding to phase error of ±0.6°and amplitude mismatch of ±1.1dB. © 2013 JSAP.

A wirelessly-powered, near-threshold, body area network SoC supporting synchronized multi-node TDMA operation is demonstrated in 65nm CMOS. A global clock source sent from a base-station wirelessly broadcasts at 434.16MHz to all sensor nodes, where each individual BAN sensor is phase-locked to the base-station clock using a super-harmonic injection-locked frequency divider. Each near-threshold SoC harvests energy from and phase locks to this broadcasted 434.16MHz waveform, eliminating the need for a battery. A Near-V-T MICS-band OOK transmitter sends the synchronized local sensor data back to the base-station in its pre-defined TDMA slot. For an energy-harvested local V-DD=0.56V, measurements demonstrate full functionality over 1.4m between the base-station and four worn sensors, including two that are NLOS. The sensitivity of the RF energy harvesting and the wireless clock synchronization are measured at -8dBm and -35dBm, respectively. ECG Lead-II / Lead-III waveforms are experimentally captured, demonstrating the end-to-end system application.