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The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work e

This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180nm CMOS process and operating with ±1.8V supply rails, the input resistance is 1.05ohms and the power dissipation is 93.6µW. The bandwidth, for a gain of 100dBohm, exceeded 9MHz. For a 1µA, 1MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09pA/√Hz and with a photodiode capacitance of 2pF is 8.52pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5pF to 2pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned.

This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180nm CMOS process and operating with ±1.8V supply rails, the input resistance is 1.05ohms and the power dissipation is 93.6µW. The bandwidth, for a gain of 100dBohm, exceeded 9MHz. For a 1µA, 1MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09pA/√Hz and with a photodiode capacitance of 2pF is 8.52pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5pF to 2pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned.

Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW of power and occupies 73*32µm2 silicon area.

The object of this research was a self-resonated inverter, based on paralleled Insulated-Gate Bipolar Transistors (IGBTs), for high-frequency induction heating equipment, operating in a wide range of output powers, applicable for research and industrial purposes. For the nominal installed capacity for these types of invertors to be improved, the presented inverter with a modified circuit comprising IGBT transistors connected in parallel was explored. The suggested topology required several engineering problems to be solved: minimisation of the current mismatch amongst the paralleled transistors; a precise analysis of the dynamic and static transistors’ parameters; determination of the derating and mismatch factors necessary for a reliable design; experimental verification confirming the applicability of the suggested topology in the investigated inverter. This paper presents the design and analysis of IGBT transistors based on datasheet parameters and mathematical apparatus application. The expected current mismatch and the necessary derating factor, based on the expected mismatch in transistor parameters in a production lot, were determined. The suggested design was experimentally tested and investigated using a self-resonant inverter model in a melting crucible induction laboratory furnace.

In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias was able to minimise threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed 0.9mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64ppm/0C. The proposed circuit consumed 5.04µW of power from a 0.45V power supply voltage. A prototype was implemented in 65nm CMOS technology occupying a 2888µm2 silicon area, with the nominal value of the reference at 261mV.

A source follower lowpass filter which has a capability of bulk-attenuation cancellation in higher order is presented. Under strong inversion bias arrangement for high frequency application, this fourth-order-filter is simulated in a 0.18 µm standard CMOS process and exhibits a 20 MHz bandwidth with total power consumption of 0.323 mW from 1.8 V supply. Third order intermodulation distortion verification with 1.9 and 2.1 MHz signal archives 23.9 dBm IIP3 with 75.5 dB dynamic range. By using figure-of-merit as a benchmark indicator, the proposed filter is one of the top in its class with the lowest power consumption.

The object of this research was a self-resonated inverter, based on paralleled Insulated-Gate Bipolar Transistors (IGBTs), for high-frequency induction heating equipment, operating in a wide range of output powers, applicable for research and industrial purposes. For the nominal installed capacity for these types of invertors to be improved, the presented inverter with a modified circuit comprising IGBT transistors connected in parallel was explored. The suggested topology required several engineering problems to be solved: minimisation of the current mismatch amongst the paralleled transistors; a precise analysis of the dynamic and static transistors’ parameters; determination of the derating and mismatch factors necessary for a reliable design; experimental verification confirming the applicability of the suggested topology in the investigated inverter. This paper presents the design and analysis of IGBT transistors based on datasheet parameters and mathematical apparatus application. The expected current mismatch and the necessary derating factor, based on the expected mismatch in transistor parameters in a production lot, were determined. The suggested design was experimentally tested and investigated using a self-resonant inverter model in a melting crucible induction laboratory furnace.

A source follower lowpass filter which has a capability of bulk-attenuation cancellation in higher order is presented. Under strong inversion bias arrangement for high frequency application, this fourth-order-filter is simulated in a 0.18 µm standard CMOS process and exhibits a 20 MHz bandwidth with total power consumption of 0.323 mW from 1.8 V supply. Third order intermodulation distortion verification with 1.9 and 2.1 MHz signal archives 23.9 dBm IIP3 with 75.5 dB dynamic range. By using figure-of-merit as a benchmark indicator, the proposed filter is one of the top in its class with the lowest power consumption.

Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW of power and occupies 73*32µm2 silicon area.

In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias was able to minimise threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed 0.9mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64ppm/0C. The proposed circuit consumed 5.04µW of power from a 0.45V power supply voltage. A prototype was implemented in 65nm CMOS technology occupying a 2888µm2 silicon area, with the nominal value of the reference at 261mV.

This thesis presents the work undertaken while carrying out research into acoustic measurement techniques for 3-dimensional acoustic radiation data for musical instruments, specifically when the instruments are being played by musicians. The original contribution to knowledge that is presented includes the development of an algorithm which can be used for post-processing of recorded data to obtain signals from ‘virtual’ microphones. The project is discussed along with a rationale for the particular test and measurement procedure used in this research and is followed by a literature review outlining both historical and current research and writing relevant to the project. A design for high spatial resolution 3-D acoustic measurement apparatus is proposed, and the design details and construction methods are discussed. The measurement process is described, including the issues surrounding testing and the use of human musicians in the measurement of musical instrument acoustic radiation patterns. A novel algorithm is presented which applies transfer functions derived from interpolated measured data points in order to process recorded audio signals with applications in audio post-production. A prototype implementation of the algorithm is described along with its testing. The conclusion summarises the thesis; contains an evaluation of the work undertaken and the results; and explores potential future work from this project.

Recent advancements in vehicle automation have led to a proliferation of studies in traffic control strategies for the next generation of land vehicles. Current traffic signal based intersection control methods have significant limitations on dealing with rapidly evolving mobility, connectivity and social challenges. Figures for Europe over the period 2007-16 show that 20% of road accidents that have fatalities occur at intersections. Connected and Automated Mobility (CAM) presents a new paradigm for the integration of radically different traffic control methods into cities and towns for increased travel time efficiency and safety. Vehicle-to-Everything (V2X) connectivity between Intelligent Transportation System (ITS) users will make a significant contribution to transforming the current signalised traffic control systems into a more cooperative and reactive control system. This research work proposes a disruptive unsignalised traffic control method using a Reinforcement Learning (RL) algorithm to determine vehicle priorities at intersections and to schedule their crossing with the objectives of reducing congestion and increasing safety. Unlike heuristic rule-based methods, RL agents can learn the complex non-linear relationship between the elements that play a key role in traffic flow, from which an optimal control policy can be obtained. This work also focuses on the data requirements that inform Vehicle-to-Infrastructure (V2I) communication needs of such a system. The proposed traffic control method has been validated on a state-of-the-art simulation tool and a comparison of results with a traditional signalised control method indicated an up to 84% and 41% improvement in terms of reducing vehicle delay times and reducing fuel consumption respectively. In addition to computer simulations, practical experiments have also been conducted on a scaled road network with a single intersection and multiple scaled Connected and Automated Vehicles (CAV) to further validat

In this paper miller compensation of opamp has been explained intuitively and discussed the problems existing with this traditional way. Proposed an area/power efficient technique by splitting the second stage has been proposed. The splitting introduces an extra zero in the transfer function such that it will improve the stability. This tech was implemented in 45nm CMOS technology and simulated with Spectre. Simulation results show that the proposed circuit saves 50% of the capacitance area compared to the miller technique. The circuit draws320uA current from 1.5V supply and occupying 0.003108mm2 silicon area.

A transformer-less Buck-Boost DC-DC converter in usage for the fast-charge of electric vehicles, based on powerful high-voltage IGBT (Isolated Gate Bipolar Transistor) modules is analyzed, designed and experimentally verified. The main advantages of this topology are: simple structure on the converter’s power stage; a wide range of the output voltage, capable to support nowadays vehicles on-board battery packs; efficiency and power density accepted to be high enough for such class of hard-switched converters. A precise estimation of the loss, dissipated in the converter’s basic modes of operation – Buck, Boost, and Buck-Boost is presented. The analysis shows an approach of loss minimization, based on switching frequency reduction during the Buck-Boost operation mode. Such a technique guarantees stable thermal characteristics during the entire operation, i.e. battery charge cycle. As the Buck-Boost mode takes place when Buck and Boost modes cannot support the output voltage, operating as a combination of them, it can be considered as critically dependent on the characteristics of the semiconductors. With this, the necessary duty cycle and voltage range, determined with respect to the input-output voltages and power losses, require additional study to be conducted. Additionally, the tolerance of the applied switching frequencies for the most versatile silicon-based powerful IGBT modules is analyzed and experimentally verified. Finally, several important characteristics, such as transients during switch-on and switch-off, IGBTs voltage tails, critical duty cycles, etc., are depicted experimentally with oscillograms, obtained by an experimental model.

The research work described in this thesis was concerned with finding a novel method of minimising motion artefacts in biomedical instrumentation systems. The proposed solution, an Analog Frontend (AFE), was designed to detect any vertical (Y-Plane) or horizontal (X-Plane) movement of the electrode using two strain gauges, which were separated by 90° and fitted onto the electrode. The detected motion was fed back to the system for the removal of any motion artefact. The research started by emphasising the importance of minimising motion artefacts from biomedical signals and explaining how important it is for a clinical misinterpretation of the results. Hence, various motion artefact minimisation techniques undertaken by other researchers in the field were reviewed. This study covered different sources of artefacts, including the 40kHz powerline interference (PLI), 50/60kHz common-mode noise, white noise, and motion artefacts. The system was fully developed and tested and was firstly simulated using MATLAB Simulink tools to prove the effectiveness of the system before starting the implementation and build phase in the lab. The AFE system successfully produced a clean output signal, achieving an average correlation coefficient of 0.995. Also, the system output had a 98% SNR similarity with the clean source signal. Further, the system was then built and tested in the lab and successfully minimised the motion artefacts, achieving an average correlation coefficient of 0.974. Additionally, the final output had a 97.8% SNR similarity with the clean source signal. A novel test rig was developed to test the system with strain gauges. The system was able to remove the detected signal from the test rig and had an average correlation coefficient of 0.957. Lastly, the final output had a 94.2% SNR similarity with the clean source signal.

The research discussed here aims to design a deep learning algorithm based on Convolutional Neural Networks models to detect driver distraction and fatigue using driver facial expressions. The proposed model provides high accuracy during both training and validation. The research was inspired to contribute to transport safety by providing alternative solutions to detect driver habit. First, the thesis discussed Conventional methods, including Haar cascade classifiers and eigenfaces. In 2018 I published a proposal for a blink rate detection system using Haar cascade feature detection. However, due to the advantages of Neural Networks, the research focused on providing a unique solution in that field. An in-depth look at how Neural Networks function, specifically Convolutional Neural Networks (CNNs), was investigated and discussed next. Due to the advantages CNN's have with feature detection in images, the algorithm I proposed in this research uses a CNN architecture. Lastly, I proposed an adaptive approach for deep learning to enhance training, validation and testing accuracies. My original algorithm and subsequent models were trained on two datasets. These were the American University in Cairo (AUC) Distracted Driver Dataset and the UTA Real-Life Drowsiness Dataset (UTA-RLDD). Hence the research proposed two original CNN models that produced high training and validation accuracy. The model designed on the AUC Distracted Driver Dataset achieved good 97% training accuracy and good 96% validation accuracy. Evaluation of this model produced good 99% accuracy. The model designed on UTA-RLDD achieved 100% training accuracy, 69% validation accuracy, and evaluated at 69% accuracy.

A transformer-less Buck-Boost DC-DC converter in usage for the fast-charge of electric vehicles, based on powerful high-voltage IGBT (Isolated Gate Bipolar Transistor) modules is analyzed, designed and experimentally verified. The main advantages of this topology are: simple structure on the converter’s power stage; a wide range of the output voltage, capable to support nowadays vehicles on-board battery packs; efficiency and power density accepted to be high enough for such class of hard-switched converters. A precise estimation of the loss, dissipated in the converter’s basic modes of operation – Buck, Boost, and Buck-Boost is presented. The analysis shows an approach of loss minimization, based on switching frequency reduction during the Buck-Boost operation mode. Such a technique guarantees stable thermal characteristics during the entire operation, i.e. battery charge cycle. As the Buck-Boost mode takes place when Buck and Boost modes cannot support the output voltage, operating as a combination of them, it can be considered as critically dependent on the characteristics of the semiconductors. With this, the necessary duty cycle and voltage range, determined with respect to the input-output voltages and power losses, require additional study to be conducted. Additionally, the tolerance of the applied switching frequencies for the most versatile silicon-based powerful IGBT modules is analyzed and experimentally verified. Finally, several important characteristics, such as transients during switch-on and switch-off, IGBTs voltage tails, critical duty cycles, etc., are depicted experimentally with oscillograms, obtained by an experimental model.

In this paper miller compensation of opamp has been explained intuitively and discussed the problems existing with this traditional way. Proposed an area/power efficient technique by splitting the second stage has been proposed. The splitting introduces an extra zero in the transfer function such that it will improve the stability. This tech was implemented in 45nm CMOS technology and simulated with Spectre. Simulation results show that the proposed circuit saves 50% of the capacitance area compared to the miller technique. The circuit draws320uA current from 1.5V supply and occupying 0.003108mm2 silicon area.

This thesis describes the research, design, manufacturing and testing of a novel multi-sensor machine monitoring system: this system integrated with existing programmable logic controller (PLC) systems and wirelessly transmitted condition data. The research began by exploring machine monitoring strategies and the individual sensor topic areas. Methods for interfacing with PLCs and microcontroller-based wireless transmission systems were also explored. Potential electrical and physical interferences in the system were identified alongside methods to minimise them. The designs were then simulated, prototyped and revised before final manufactured designs were practically tested on factory machines. The Clutch and Brake (C&B) sensor measured the wear of the pads in 0.08cm windows with a minimum detectable increment of 0.02cm. The C&B sensors total range was 26cm which meant the sensor could measure to a resolution of 0.08% of its total range with a sensitivity of 0.27V/cm. The wear conditions were correctly reported to the PLC which activated the programmed corrective actions. The Vibration Analysis (VA) sensor measured vibration in different motors and highlighted mechanical looseness in a motor which had recently undergone maintenance. The bandwidth of the VA sensor was 1kHz with an amplitude of acceleration within the ±16g range. The resolution of the acceleration measurement was 3.9mg which was 0.02% of the established 20g measuring range. The conditions of the motors were determined by programming which was precise to 3dp. The Non-Intrusive Pipe Pressure (NIPP) sensor monitored the pressure inside a pipe in 10bar brackets which equated to 18mV: the entire sensor range covered 0.18V which was only 3.6% of the available microcontroller range. This allowed a clear press pressure cycle to be graphically displayed from the NIPP sensor data. A leak was simulated in the PLC program and the pumps were promptly shutdown as intended. All the sensors wirelessly transmitted th

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply.

This thesis is concerned with the design of a polyhedron enumeration algorithm. The approach taken focuses on specic classes of polyhedra and their graph theoretic properties. This is then compared more broadly to other graph enumeration algorithms that are concerned with the same or a superset which includes these properties. An original and novel algorithm is contributed to this area. The approach taken divides the problem into prescribed vertex and face degree sequences for the graphs. Using a range of existence, ordered enumeration and isomorphism techniques, it finds all unique 4-regular, 3-connected planar graphs. The algorithm is a vertex addition algorithm which means that each result output at a given stage has a new vertex added. Other results from different stages are never required for further computation and comparison, hence the process is embarrassingly parallel. Therefore, the enumeration can be distributed optimally across a cluster of computers. This work has led to a successfully implemented algorithm which takes a different approach to its treatment of the class of 4-regular, 3-connected planar graphs. As such this has led to observations and theory about other classes of graphs and graph embeddings which relate to this research.

This thesis is concerned with the design of a polyhedron enumeration algorithm. The approach taken focuses on specic classes of polyhedra and their graph theoretic properties. This is then compared more broadly to other graph enumeration algorithms that are concerned with the same or a superset which includes these properties. An original and novel algorithm is contributed to this area. The approach taken divides the problem into prescribed vertex and face degree sequences for the graphs. Using a range of existence, ordered enumeration and isomorphism techniques, it finds all unique 4-regular, 3-connected planar graphs. The algorithm is a vertex addition algorithm which means that each result output at a given stage has a new vertex added. Other results from different stages are never required for further computation and comparison, hence the process is embarrassingly parallel. Therefore, the enumeration can be distributed optimally across a cluster of computers. This work has led to a successfully implemented algorithm which takes a different approach to its treatment of the class of 4-regular, 3-connected planar graphs. As such this has led to observations and theory about other classes of graphs and graph embeddings which relate to this research.

Autonomous vehicles have been shown to increase safety for drivers, passengers and pedestrians and can also be used to maximize traffic flow, thereby reducing emissions and congestion. At the same time, governments around the world are promoting the usage of Battery Electric Vehicles (BEVs) to reduce and control the emissions of CO2. This has made the development of autonomous vehicles and electric vehicles a very active research area and has prompted a significant amount of government funding. This paper presents the detailed design of a low-cost platform for the development of an autonomous electric vehicle. In particular, it focuses on the design of the electrical architecture and the control strategy, tailored around the usage of affordable sensors and actuators. The specifications of the components are extensively discussed in relation to the performance target. The aim is to provide a comprehensive guide for the development of the remotely controlled platform, in order to lower the entry barrier for the development of autonomous electric vehicles.

[Paper presented at the Institute of Acoustics 2019 Conference, held in Milton Keynes, 13-14 May 2019.]

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply.

Integrated low noise neural amplifiers become recently practical in CMOS technologies. In this paper, a low noise OTA technique has been proposed while keeping the power consumption constant. A capacitive feedback, ac coupled 46dB amplifier with high pass cutoff frequency close to the 90Hz has been achieved. The proposed amplifier has been implemented in 65nm CMOS technology; at room temperature circuit consumes 323uA current from 1.2V power supply. The circuit occupies 2627um 2 silicon area.

This paper explains the hidden positive feedback in the two-stage fully differential amplifier through external feedback resistors, and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascode branches have been explained intuitively, With reference to previous literature. To avoid the latch-up problem irrespective of the transistor bias currents a novel, hysteresis based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126uA from a 1.2V supply and occupies the 2184um2 area.

The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of − 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um2 silicon area.

A sub-threshold MOS based pseudo resistor featuring a very high value and ultra-low distortion is proposed. A band-pass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The stand-alone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31dB mid-band gain and a lowpass cutoff frequency of 0.85Hz. The circuit operates from a 1V supply and draws 950nA current at room temperature.

This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high frequency common mode interference. A modified 3-OTA IA has been proposed to help with the impedance measurement. Such systems offer a quick, non-invasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65nm CMOS technology and post layout simulations confirms the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45uW from 1.5V power supply. The circuit occupies 0.01954mm2 silicon area.

This paper presents a fully integrated Front-end, low noise amplifier, dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input referred noise of the Low Noise Amplifier (LNA), without adding any additional power. The proposed technique implemented in 65nm CMOS technology achieves 30dB closed loop voltage gain, 0.05Hz lower cut-off frequency and 100MHz 3-dB bandwidth. It operates at 1.2V power supply and draws 1µA static current. The prototype described in this paper occupies 3300µm2silicon area.

Capturing a near-perfect, artefact free signal is an ideal of biomedicine. However, this depends on the removal of different types of artefact, all of which can be considered unwanted noise on the desired signal. Failure to remove artefacts could lead to a clinical misinterpretation of the results. All medical equipment such as electrocardiogram systems which use electrodes attached to patients suffer from artefacts, with effects ranging from minor blurring to significant distortion of the output signal(s). For this reason, it is important to identify how artefacts can influence the output signal. In this paper, we propose a new technique to detect and minimise movement artefacts using strain gauges embedded into the electrodes.

In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55° phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2 silicon area.

In this paper a low opamp compensation technique suitable for the bio-medical application has been proposed and intuitive explained the existing compensation techniques. The Present technique relies on the passive damping factor control rather power hungry damping. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that 100dB dc gain, well compensated 25MHz bandwidth opamp while driving a 1pF capacitive load. Draws with 12uW power consumption from 1V supply and occupying 0.004875mm2 silicon area.

This paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130uA from a 1.2V power supply.

This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with existing BJT-based reference circuits, by using a MOS transistor operating in subthreshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55V, and generates a 286mV reference voltage with a temperature coefficient of 59ppm/°C. The circuit takes 413nA current from 0.55V supply and occupies 0.00986mm2 of active area

A sub-threshold MOS based pseudo resistor featuring a very high value and ultra-low distortion is proposed. A band-pass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The stand-alone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31dB mid-band gain and a lowpass cutoff frequency of 0.85Hz. The circuit operates from a 1V supply and draws 950nA current at room temperature.

Capturing a near-perfect, artefact free signal is an ideal of biomedicine. However, this depends on the removal of different types of artefact, all of which can be considered unwanted noise on the desired signal. Failure to remove artefacts could lead to a clinical misinterpretation of the results. All medical equipment such as electrocardiogram systems which use electrodes attached to patients suffer from artefacts, with effects ranging from minor blurring to significant distortion of the output signal(s). For this reason, it is important to identify how artefacts can influence the output signal. In this paper, we propose a new technique to detect and minimise movement artefacts using strain gauges embedded into the electrodes.

The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of − 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um2 silicon area.

This paper presents a fully integrated Front-end, low noise amplifier, dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input referred noise of the Low Noise Amplifier (LNA), without adding any additional power. The proposed technique implemented in 65nm CMOS technology achieves 30dB closed loop voltage gain, 0.05Hz lower cut-off frequency and 100MHz 3-dB bandwidth. It operates at 1.2V power supply and draws 1µA static current. The prototype described in this paper occupies 3300µm2silicon area.

This paper explains the hidden positive feedback in the two-stage fully differential amplifier through external feedback resistors, and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascode branches have been explained intuitively, With reference to previous literature. To avoid the latch-up problem irrespective of the transistor bias currents a novel, hysteresis based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126uA from a 1.2V supply and occupies the 2184um2 area.

This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high frequency common mode interference. A modified 3-OTA IA has been proposed to help with the impedance measurement. Such systems offer a quick, non-invasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65nm CMOS technology and post layout simulations confirms the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45uW from 1.5V power supply. The circuit occupies 0.01954mm2 silicon area.

In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55° phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2 silicon area.

This paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130uA from a 1.2V power supply.

Intersection control has an important role in the management of urban traffic to ensure safety, high traffic flow and to prevent congestion. Recently, a growing body of literature has been reported on the theme of non-signalised intersection control in which traffic lights are replaced with intelligent road side units. Data from several studies suggest that non-signalised control could reduce vehicle delays and fuel consumption significantly whilst ensuring safety. However, there is little published data on the impact of the mixed driving behaviour with human-driven vehicles and autonomous vehicles. This paper investigates the emerging role of connectivity and vehicle autonomy in the context of traffic control under the mixed driving behaviour scenario. The concepts of vehicle-to-infrastructure (V2I) communications and multi-agent systems are central to achieving a robust and reliable traffic-light-free intersection control. Comprehensive computer simulation results on a four-way intersection indicate over 96% reduced average vehicle delay and 37% less fuel consumption with the non-signalised control solution compared to the traffic light control. The outcome of this study offers some important insights into enabling cooperation between vehicles and traffic infrastructure via V2I communications, in order to make more efficient real-time decisions about traffic conditions, whilst ensuring a higher degree of safety.

This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with existing BJT-based reference circuits, by using a MOS transistor operating in subthreshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55V, and generates a 286mV reference voltage with a temperature coefficient of 59ppm/°C. The circuit takes 413nA current from 0.55V supply and occupies 0.00986mm2 of active area

Integrated low noise neural amplifiers become recently practical in CMOS technologies. In this paper, a low noise OTA technique has been proposed while keeping the power consumption constant. A capacitive feedback, ac coupled 46dB amplifier with high pass cutoff frequency close to the 90Hz has been achieved. The proposed amplifier has been implemented in 65nm CMOS technology; at room temperature circuit consumes 323uA current from 1.2V power supply. The circuit occupies 2627um 2 silicon area.

In this paper a low opamp compensation technique suitable for the bio-medical application has been proposed and intuitive explained the existing compensation techniques. The Present technique relies on the passive damping factor control rather power hungry damping. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that 100dB dc gain, well compensated 25MHz bandwidth opamp while driving a 1pF capacitive load. Draws with 12uW power consumption from 1V supply and occupying 0.004875mm2 silicon area.

This paper proposes a technique to detect Leukaemia (blood cancer) based on the frequency modulation of a relaxation oscillator by changes in the dielectric constant of blood cells. A novel 16-bit frequency detector with a digital output has been proposed to detect the frequency difference between two oscillators based on healthy blood and Leukaemic blood. A circuit has been designed, to operate on a 1.2V supply, post layout simulations shows 0.35mA current consumption. The chip Area including pads~0.6mm∗0.45mm