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As is well-known, defects precisely affect the lives and functions of the machines in which they occur, and even cause potentially catastrophic casualties. Therefore, quality assessment before mounting is an indispensable requirement for factories. Apart from the recognition accuracy, current networks suffer from excessive computing complexity, making it of great difficulty to deploy in the manufacturing process. To address these issues, this paper introduces binary networks into the area of surface defect detection for the first time, for the reason that binary networks prohibitively constrain weight and activation to +1 and −1. The proposed Bi-ShuffleNet and U-BiNet utilize binary convolution layers and activations in low bitwidth, in order to reach comparable performances while incurring much less computational cost. Extensive experiments are conducted on real-life NEU and Magnetic Tile datasets, revealing the least OPs required and little accuracy decline. When classifying the defects, Bi-ShuffleNet yields comparable results to counterpart networks, with at least 2× inference complexity reduction. Defect segmentation results indicate similar observations. Some network design rules in defect detection and binary networks are also summarized in this paper.

This thesis introduces novel frameworks for automated customization of two classes of machine learning algorithms, deep neural networks and causal Bayesian analysis. The high computational complexity often prohibits the deployment of ML models on resource-constrained embedded devices where memory and energy budgets are strictly limited. FPGAs offer a flexible substrate that can be configured to maximally exploit the parallel nature of computations in different ML algorithms to deliver high-throughput and power-efficient accelerators. To make FPGAs a ubiquitous platform for ML inference, automated frameworks that can customize ML models to the constraints of the underlying hardware and pertinent application requirements are necessary. My work proposes hardware-algorithm co-design approaches to customize ML inference on FPGA platforms and provides end-to-end automated frameworks to generate optimized hardware accelerators which can be used by a broad range of ML developers without requiring any hardware design knowledge. My key contributions include: (i) proposing an end-to-end framework to customize execution of deep neural networks on FPGAs using a reconfigurable encoding approach for the parameters of model which results in 9-fold reduction in memory footprint and 15-fold improvement in throughput without any loss in accuracy, (ii) proposing CausaLearn, the first automated framework that enables real-time and scalable approximation of probability density function in the context of causal Bayesian analysis which offers up to two orders-of-magnitude runtime and energy improvements compared to the best-known prior solution, (iii) proposing ReBNet, an end-to-end framework for training reconfigurable binary neural networks on software and developing efficient accelerators for execution on FPGA.

This thesis introduces novel frameworks for automated customization of two classes of machine learning algorithms, deep neural networks and causal Bayesian analysis. The high computational complexity often prohibits the deployment of ML models on resource-constrained embedded devices where memory and energy budgets are strictly limited. FPGAs offer a flexible substrate that can be configured to maximally exploit the parallel nature of computations in different ML algorithms to deliver high-throughput and power-efficient accelerators. To make FPGAs a ubiquitous platform for ML inference, automated frameworks that can customize ML models to the constraints of the underlying hardware and pertinent application requirements are necessary. My work proposes hardware-algorithm co-design approaches to customize ML inference on FPGA platforms and provides end-to-end automated frameworks to generate optimized hardware accelerators which can be used by a broad range of ML developers without requiring any hardware design knowledge. My key contributions include: (i) proposing an end-to-end framework to customize execution of deep neural networks on FPGAs using a reconfigurable encoding approach for the parameters of model which results in 9-fold reduction in memory footprint and 15-fold improvement in throughput without any loss in accuracy, (ii) proposing CausaLearn, the first automated framework that enables real-time and scalable approximation of probability density function in the context of causal Bayesian analysis which offers up to two orders-of-magnitude runtime and energy improvements compared to the best-known prior solution, (iii) proposing ReBNet, an end-to-end framework for training reconfigurable binary neural networks on software and developing efficient accelerators for execution on FPGA.