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The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enhance reliability, and mitigate security vulnerability. Nonetheless, DRAM manufacturers have disclosed only a limited amount of information, making it difficult to find specific information on their DRAM microarchitectures. This paper addresses this gap by presenting more rigorous findings on the microarchitectures of commodity DRAM chips and their impacts on the characteristics of activate-induced bitflips (AIBs), such as RowHammer and RowPress. The previous studies have also attempted to understand the DRAM microarchitectures and associated behaviors, but we have found some of their results to be misled by inaccurate address mapping and internal data swizzling, or lack of a deeper understanding of the modern DRAM cell structure. For accurate and efficient reverse-engineering, we use three tools: AIBs, retention time test, and RowCopy, which can be cross-validated. With these three tools, we first take a macroscopic view of modern DRAM chips to uncover the size, structure, and operation of their subarrays, memory array tiles (MATs), and rows. Then, we analyze AIB characteristics based on the microscopic view of the DRAM microarchitecture, such as 6F^2 cell layout, through which we rectify misunderstandings regarding AIBs and discover a new data pattern that accelerates AIBs. Lastly, based on our findings at both macroscopic and microscopic levels, we identify previously unknown AIB vulnerabilities and propose a simple yet effective protection solution., Comment: To appear at the 51st IEEE/ACM International Symposium on Computer Architecture (ISCA)

Convolutional neural network (CNN) inference using fully homomorphic encryption (FHE) is a promising private inference (PI) solution due to the capability of FHE that enables offloading the whole computation process to the server while protecting the privacy of sensitive user data. Prior FHE-based CNN (HCNN) work has demonstrated the feasibility of constructing deep neural network architectures such as ResNet using FHE. Despite these advancements, HCNN still faces significant challenges in practicality due to the high computational and memory overhead. To overcome these limitations, we present HyPHEN, a deep HCNN construction that incorporates novel convolution algorithms (RAConv and CAConv), data packing methods (2D gap packing and PRCR scheme), and optimization techniques tailored to HCNN construction. Such enhancements enable HyPHEN to substantially reduce the memory footprint and the number of expensive homomorphic operations, such as ciphertext rotation and bootstrapping. As a result, HyPHEN brings the latency of HCNN CIFAR-10 inference down to a practical level at 1.4 seconds (ResNet-20) and demonstrates HCNN ImageNet inference for the first time at 14.7 seconds (ResNet-18)., Comment: 15 pages, 12 figures

The demand for accurate information about the internal structure and characteristics of dynamic random-access memory (DRAM) has been on the rise. Recent studies have explored the structure and characteristics of DRAM to improve processing in memory, enhance reliability, and mitigate a vulnerability known as rowhammer. However, DRAM manufacturers only disclose limited information through official documents, making it difficult to find specific information about actual DRAM devices. This paper presents reliable findings on the internal structure and characteristics of DRAM using activate-induced bitflips (AIBs), retention time test, and row-copy operation. While previous studies have attempted to understand the internal behaviors of DRAM devices, they have only shown results without identifying the causes or have analyzed DRAM modules rather than individual chips. We first uncover the size, structure, and operation of DRAM subarrays and verify our findings on the characteristics of DRAM. Then, we correct misunderstood information related to AIBs and demonstrate experimental results supporting the cause of rowhammer. We expect that the information we uncover about the structure, behavior, and characteristics of DRAM will help future DRAM research., Comment: 4 pages, 7 figures, accepted at IEEE Computer Architecture Letters

The ever-growing demands for memory with larger capacity and higher bandwidth have driven recent innovations on memory expansion and disaggregation technologies based on Compute eXpress Link (CXL). Especially, CXL-based memory expansion technology has recently gained notable attention for its ability not only to economically expand memory capacity and bandwidth but also to decouple memory technologies from a specific memory interface of the CPU. However, since CXL memory devices have not been widely available, they have been emulated using DDR memory in a remote NUMA node. In this paper, for the first time, we comprehensively evaluate a true CXL-ready system based on the latest 4th-generation Intel Xeon CPU with three CXL memory devices from different manufacturers. Specifically, we run a set of microbenchmarks not only to compare the performance of true CXL memory with that of emulated CXL memory but also to analyze the complex interplay between the CPU and CXL memory in depth. This reveals important differences between emulated CXL memory and true CXL memory, some of which will compel researchers to revisit the analyses and proposals from recent work. Next, we identify opportunities for memory-bandwidth-intensive applications to benefit from the use of CXL memory. Lastly, we propose a CXL-memory-aware dynamic page allocation policy, Caption to more efficiently use CXL memory as a bandwidth expander. We demonstrate that Caption can automatically converge to an empirically favorable percentage of pages allocated to CXL memory, which improves the performance of memory-bandwidth-intensive applications by up to 24% when compared to the default page allocation policy designed for traditional NUMA systems., Comment: This paper has been accepted by MICRO'23. Please refer to the https://doi.org/10.1145/3613424.3614256 for the official version of this paper

Fully homomorphic encryption (FHE) is a promising cryptographic primitive for realizing private neural network inference (PI) services by allowing a client to fully offload the inference task to a cloud server while keeping the client data oblivious to the server. This work proposes NeuJeans, an FHE-based solution for the PI of deep convolutional neural networks (CNNs). NeuJeans tackles the critical problem of the enormous computational cost for the FHE evaluation of convolutional layers (conv2d), mainly due to the high cost of data reordering and bootstrapping. We first propose an encoding method introducing nested structures inside encoded vectors for FHE, which enables us to develop efficient conv2d algorithms with reduced data reordering costs. However, the new encoding method also introduces additional computations for conversion between encoding methods, which could negate its advantages. We discover that fusing conv2d with bootstrapping eliminates such computations while reducing the cost of bootstrapping. Then, we devise optimized execution flows for various types of conv2d and apply them to end-to-end implementation of CNNs. NeuJeans accelerates the performance of conv2d by up to 5.68 times compared to state-of-the-art FHE-based PI work and performs the PI of a CNN at the scale of ImageNet (ResNet18) within a mere few seconds, Comment: 16 pages, 9 figures

Incorporating fully homomorphic encryption (FHE) into the inference process of a convolutional neural network (CNN) draws enormous attention as a viable approach for achieving private inference (PI). FHE allows delegating the entire computation process to the server while ensuring the confidentiality of sensitive client-side data. However, practical FHE implementation of a CNN faces significant hurdles, primarily due to FHE's substantial computational and memory overhead. To address these challenges, we propose a set of optimizations, which includes GPU/ASIC acceleration, an efficient activation function, and an optimized packing scheme. We evaluate our method using the ResNet models on the CIFAR-10 and ImageNet datasets, achieving several orders of magnitude improvement compared to prior work and reducing the latency of the encrypted CNN inference to 1.4 seconds on an NVIDIA A100 GPU. We also show that the latency drops to a mere 0.03 seconds with a custom hardware design., Comment: 3 pages, 1 figure, appears at DISCC 2023 (2nd Workshop on Data Integrity and Secure Cloud Computing, in conjunction with the 56th International Symposium on Microarchitecture (MICRO 2023))

Fully homomorphic encryption (FHE) is in the spotlight as a definitive solution for privacy, but the high computational overhead of FHE poses a challenge to its practical adoption. Although prior studies have attempted to design ASIC accelerators to mitigate the overhead, their designs require excessive chip resources (e.g., areas) to contain and process massive data for FHE operations. We propose CiFHER, a chiplet-based FHE accelerator with a resizable structure, to tackle the challenge with a cost-effective multi-chip module (MCM) design. First, we devise a flexible core architecture whose configuration is adjustable to conform to the global organization of chiplets and design constraints. Its distinctive feature is a composable functional unit providing varying computational throughput for the number-theoretic transform, the most dominant function in FHE. Then, we establish generalized data mapping methodologies to minimize the interconnect overhead when organizing the chips into the MCM package in a tiled manner, which becomes a significant bottleneck due to the packaging constraints. This study demonstrates that a CiFHER package composed of a number of compact chiplets provides performance comparable to state-of-the-art monolithic ASIC accelerators while significantly reducing the package-wide power consumption and manufacturing cost., Comment: 12 pages, 10 figures, to appear in 2024 International Symposium on Secure and Private Execution Environment Design (SEED)

We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off- and on- stack bandwidth requirements at acceptable power levels. Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memory-intensive workloads, while simultaneously reducing power., Comment: This edition is recompiled from proceedings of ISCA-35 (the 35th International Symposium on Computer Architecture, June 21 - 25, 2008, Beijing, China) and has minor formatting differences. 13 pages; 11 figures

The 2008 Corona effort was inspired by a pressing need for more of everything, as demanded by the salient problems of the day. Dennard scaling was no longer in effect. A lot of computer architecture research was in the doldrums. Papers often showed incremental subsystem performance improvements, but at incommensurate cost and complexity. The many-core era was moving rapidly, and the approach with many simpler cores was at odds with the better and more complex subsystem publications of the day. Core counts were doubling every 18 months, while per-pin bandwidth was expected to double, at best, over the next decade. Memory bandwidth and capacity had to increase to keep pace with ever more powerful multi-core processors. With increasing core counts per die, inter-core communication bandwidth and latency became more important. At the same time, the area and power of electrical networks-on-chip were increasingly problematic: To be reliably received, any signal that traverses a wire spanning a full reticle-sized die would need significant equalization, re-timing, and multiple clock cycles. This additional time, area, and power was the crux of the concern, and things looked to get worse in the future. Silicon nanophotonics was of particular interest and seemed to be improving rapidly. This led us to consider taking advantage of 3D packaging, where one die in the 3D stack would be a photonic network layer. Our focus was on a system that could be built about a decade out. Thus, we tried to predict how the technologies and the system performance requirements would converge in about 2018. Corona was the result this exercise; now, 15 years later, it's interesting to look back at the effort., Comment: 2 pages. Proceedings of ISCA-50: 50 years of the International Symposia on Computer Architecture (selected papers) June 17-21 Orlando, Florida

Homomorphic Encryption (HE) is one of the most promising post-quantum cryptographic schemes that enable privacy-preserving computation on servers. However, noise accumulates as we perform operations on HE-encrypted data, restricting the number of possible operations. Fully HE (FHE) removes this restriction by introducing the bootstrapping operation, which refreshes the data; however, FHE schemes are highly memory-bound. Bootstrapping, in particular, requires loading GBs of evaluation keys and plaintexts from off-chip memory, which makes FHE acceleration fundamentally bottlenecked by the off-chip memory bandwidth. In this paper, we propose ARK, an Accelerator for FHE with Runtime data generation and inter-operation Key reuse. ARK enables practical FHE workloads with a novel algorithm-architecture co-design to accelerate bootstrapping. We first eliminate the off-chip memory bandwidth bottleneck through runtime data generation and inter-operation key reuse. This approach enables ARK to fully exploit on-chip memory by substantially reducing the size of the working set. On top of such algorithmic enhancements, we build ARK microarchitecture that minimizes on-chip data movement through an efficient, alternating data distribution policy based on the data access patterns and a streamlined dataflow organization of the tailored functional units -- including base conversion, number-theoretic transform, and automorphism units. Overall, our co-design effectively handles the heavy computation and data movement overheads of FHE, drastically reducing the cost of HE operations, including bootstrapping., Comment: 18 pages, 9 figures

Hybrid private inference (PI) protocol, which synergistically utilizes both multi-party computation (MPC) and homomorphic encryption, is one of the most prominent techniques for PI. However, even the state-of-the-art PI protocols are bottlenecked by the non-linear layers, especially the activation functions. Although a standard non-linear activation function can generate higher model accuracy, it must be processed via a costly garbled-circuit MPC primitive. A polynomial activation can be processed via Beaver's multiplication triples MPC primitive but has been incurring severe accuracy drops so far. In this paper, we propose an accuracy preserving low-degree polynomial activation function (AESPA) that exploits the Hermite expansion of the ReLU and basis-wise normalization. We apply AESPA to popular ML models, such as VGGNet, ResNet, and pre-activation ResNet, to show an inference accuracy comparable to those of the standard models with ReLU activation, achieving superior accuracy over prior low-degree polynomial studies. When applied to the all-RELU baseline on the state-of-the-art Delphi PI protocol, AESPA shows up to 42.1x and 28.3x lower online latency and communication cost., Comment: 11 pages, 5 figures

Homomorphic encryption (HE) enables the secure offloading of computations to the cloud by providing computation on encrypted data (ciphertexts). HE is based on noisy encryption schemes in which noise accumulates as more computations are applied to the data. The limited number of operations applicable to the data prevents practical applications from exploiting HE. Bootstrapping enables an unlimited number of operations or fully HE (FHE) by refreshing the ciphertext. Unfortunately, bootstrapping requires a significant amount of additional computation and memory bandwidth as well. Prior works have proposed hardware accelerators for computation primitives of FHE. However, to the best of our knowledge, this is the first to propose a hardware FHE accelerator that supports bootstrapping as a first-class citizen. In particular, we propose BTS - Bootstrappable, Technologydriven, Secure accelerator architecture for FHE. We identify the challenges of supporting bootstrapping in the accelerator and analyze the off-chip memory bandwidth and computation required. In particular, given the limitations of modern memory technology, we identify the HE parameter sets that are efficient for FHE acceleration. Based on the insights gained from our analysis, we propose BTS, which effectively exploits the parallelism innate in HE operations by arranging a massive number of processing elements in a grid. We present the design and microarchitecture of BTS, including a network-on-chip design that exploits a deterministic communication pattern. BTS shows 5,556x and 1,306x improved execution time on ResNet-20 and logistic regression over a CPU, with a chip area of 373.6mm^2 and up to 163.2W of power., Comment: 15 pages, 10 figures

Since its public introduction in the mid-2010s, the Row Hammer (RH) phenomenon has drawn significant attention from the research community due to its security implications. Although many RH-protection schemes have been proposed by processor vendors, DRAM manufacturers, and academia, they still have shortcomings. Solutions implemented in the memory controller (MC) incur increasingly higher costs due to their conservative design for the worst case in terms of the number of DRAM banks and RH threshold to support. Meanwhile, DRAM-side implementation either has a limited time margin for RH-protection measures or requires extensive modifications to the standard DRAM interface. Recently, a new command for RH-protection has been introduced in the DDR5/LPDDR5 standards, referred to as refresh management (RFM). RFM enables the separation of the tasks for RHprotection to both MC and DRAM by having the former generate an RFM command at a specific activation frequency and the latter take proper RH-protection measures within a given time window. Although promising, no existing study presents and analyzes RFM-based solutions for RH-protection. In this paper, we propose Mithril, the first RFM interfacecompatible, DRAM-MC cooperative RH-protection scheme providing deterministic protection guarantees. Mithril has minimal energy overheads for common use cases without adversarial memory access patterns. We also introduce Mithril+, an optional extension to provide minimal performance overheads at the expense of a tiny modification to the MC, while utilizing existing DRAM commands., Comment: 16 pages, to appear in HPCA 2022

Homomorphic Encryption (HE) draws a significant attention as a privacy-preserving way for cloud computing because it allows computation on encrypted messages called ciphertexts. Among numerous HE schemes proposed, HE for Arithmetic of Approximate Numbers (HEAAN) is rapidly gaining popularity across a wide range of applications because it supports messages that can tolerate approximate computation with no limit on the number of arithmetic operations applicable to the corresponding ciphertexts. A critical shortcoming of HE is the high computation complexity of ciphertext arithmetic; especially, HE multiplication (HE Mul) is more than 10,000 times slower than the corresponding multiplication between unencrypted messages. This leads to a large body of HE acceleration studies, including ones exploiting FPGAs; however, those did not conduct a rigorous analysis of computational complexity and data access patterns of HE Mul. Moreover, the proposals mostly focused on designs with small parameter sizes, making it difficult to accurately estimate their performance in conducting a series of complex arithmetic operations. In this paper, we first describe how HE Mul of HEAAN is performed in a manner friendly to computer architects. Then we conduct a disciplined analysis on its computational and memory access characteristics, through which we (1) extract parallelism in the key functions composing HE Mul and (2) demonstrate how to effectively map the parallelism to the popular parallel processing platforms, multicore CPUs and GPUs, by applying a series of optimization techniques such as transposing matrices and pinning data to threads. This leads to the performance improvement of HE Mul on a CPU and a GPU by 42.9x and 134.1x, respectively, over the single-thread reference HEAAN running on a CPU. The conducted analysis and optimization would set a new foundation for future HE acceleration research.

Homomorphic encryption (HE) draws huge attention as it provides a way of privacy-preserving computations on encrypted messages. Number Theoretic Transform (NTT), a specialized form of Discrete Fourier Transform (DFT) in the finite field of integers, is the key algorithm that enables fast computation on encrypted ciphertexts in HE. Prior works have accelerated NTT and its inverse transformation on a popular parallel processing platform, GPU, by leveraging DFT optimization techniques. However, these GPU-based studies lack a comprehensive analysis of the primary differences between NTT and DFT or only consider small HE parameters that have tight constraints in the number of arithmetic operations that can be performed without decryption. In this paper, we analyze the algorithmic characteristics of NTT and DFT and assess the performance of NTT when we apply the optimizations that are commonly applicable to both DFT and NTT on modern GPUs. From the analysis, we identify that NTT suffers from severe main-memory bandwidth bottleneck on large HE parameter sets. To tackle the main-memory bandwidth issue, we propose a novel NTT-specific on-the-fly root generation scheme dubbed on-the-fly twiddling (OT). Compared to the baseline radix-2 NTT implementation, after applying all the optimizations, including OT, we achieve 4.2x speedup on a modern GPU., Comment: 12 pages, 13 figures, to appear in IISWC 2020

Batch Normalization (BN) has become a core design block of modern Convolutional Neural Networks (CNNs). A typical modern CNN has a large number of BN layers in its lean and deep architecture. BN requires mean and variance calculations over each mini-batch during training. Therefore, the existing memory access reduction techniques, such as fusing multiple CONV layers, are not effective for accelerating BN due to their inability to optimize mini-batch related calculations during training. To address this increasingly important problem, we propose to restructure BN layers by first splitting a BN layer into two sub-layers (fission) and then combining the first sub-layer with its preceding CONV layer and the second sub-layer with the following activation and CONV layers (fusion). The proposed solution can significantly reduce main-memory accesses while training the latest CNN models, and the experiments on a chip multiprocessor show that the proposed BN restructuring can improve the performance of DenseNet-121 by 25.7%., Comment: 13 pages, 8 figures, to appear in SysML 2019, added ResNet-50 results

The design complexity of CNNs has been steadily increasing to improve accuracy. To cope with the massive amount of computation needed for such complex CNNs, the latest solutions utilize blocking of an image over the available dimensions and batching of multiple input images to improve data reuse in the memory hierarchy. While there has been numerous works on maximizing data reuse, only a few studies have focused on the memory bottleneck caused by limited bandwidth. Bandwidth bottleneck can easily occur in CNN acceleration as CNN layers have different sizes with varying computation needs and as batching is typically performed over each CNN layer for an ideal data reuse. In this case, the data transfer demand for a layer can be relatively low or high compared to the computation requirement of the layer, and hence temporal fluctuations in memory access can be induced eventually causing bandwidth problems. In this paper, we first show that there exists a high degree of fluctuation in memory access to computation ratio depending on CNN layers and functions in the layer being processed by the compute units (cores), where the units are tightly synchronized to maximize data reuse. Then we propose a strategy of partitioning the compute units where the cores within each partition process a batch of input data synchronously to maximize data reuse but different partitions run asynchronously. As the partitions stay asynchronous and typically process different CNN layers at any given moment, the memory access traffic sizes of the partitions become statistically shuffled. Thus, the partitioning of compute units and asynchronous use of them make the total memory access traffic size be smoothened over time. We call this smoothing statistical memory traffic shaping, and we show that it can lead to 8.0 percent of performance gain on a commercial 64-core processor when running ResNet-50., Comment: 4 pages, 6 figures, appears at IEEE Computer Architecture Letters

3D-stacked DRAM has the potential to provide high performance and large capacity memory for future high performance computing systems and datacenters, and the integration of a dedicated logic die opens up opportunities for architectural enhancements such as DRAM row-buffer caches. However, high performance and cost-effective row-buffer cache designs remain challenging for 3D memory systems. In this paper, we propose History-Assisted Adaptive-Granularity Cache (HAAG$) that employs an adaptive caching scheme to support full associativity at various granularities, and an intelligent history-assisted predictor to support a large number of banks in 3D memory systems. By increasing the row-buffer cache hit rate and avoiding unnecessary data caching, HAAG$ significantly reduces memory access latency and dynamic power. Our design works particularly well for manycore CPUs running (irregular) memory intensive applications where memory locality is hard to exploit. Evaluation results show that with memory-intensive CPU workloads, HAAG$ can outperform the state-of-the-art row buffer cache by 33.5%.

Ti6Na2O13·nH2O and Ti6Na2O13 nanowires were synthesized by a hydrothermal method. The synthesized Ti6Na2O13 nanowires were used as anode materials for Li-ion cells to examine Li-storage property. The preliminary result shows that this material exhibited a discharge capacity of 1635 mAh/g at first cycle and >1050 mAh/g after second cycle. The Ti6Na2O13 nanowire electrode also showed good property retention upon cycling.

Ti6Na2O13·nH2O and Ti6Na2O13 nanowires were synthesized by a hydrothermal method. The synthesized Ti6Na2O13 nanowires were used as anode materials for Li-ion cells to examine Li-storage property. The preliminary result shows that this material exhibited a discharge capacity of 1635 mAh/g at first cycle and >1050 mAh/g after second cycle. The Ti6Na2O13 nanowire electrode also showed good property retention upon cycling.

Ti6Na2O13·nH2O and Ti6Na2O13 nanowires were synthesized by a hydrothermal method. The synthesized Ti6Na2O13 nanowires were used as anode materials for Li-ion cells to examine Li-storage property. The preliminary result shows that this material exhibited a discharge capacity of 1635 mAh/g at first cycle and >1050 mAh/g after second cycle. The Ti6Na2O13 nanowire electrode also showed good property retention upon cycling.

Nanosize carbon-supported Pt1−xCox (x = 0.2, 0.3, and 0.45) electrocatalysts were prepared by a chemical reduction method using sodium borohydride (NaBH4) as the reduction agent. Transmission electron microscopy examination showed uniform dispersion of Pt1−xCox alloy catalysts on carbon matrix, with the particle size less than 10 nm. The electrochemical characteristics of Pt1−xCox alloy catalysts were studied by cyclic voltammetry, linear sweep voltammetry, and chronoamperometric testing. The as-prepared Pt1−xCox alloy nanoparticles could be promising cathode catalysts for oxygen reduction in proton exchange membrane fuel cells with the feature of much reduced cost, but significantly increased catalytic activity.

Nanosize carbon-supported Pt1−xCox (x = 0.2, 0.3, and 0.45) electrocatalysts were prepared by a chemical reduction method using sodium borohydride (NaBH4) as the reduction agent. Transmission electron microscopy examination showed uniform dispersion of Pt1−xCox alloy catalysts on carbon matrix, with the particle size less than 10 nm. The electrochemical characteristics of Pt1−xCox alloy catalysts were studied by cyclic voltammetry, linear sweep voltammetry, and chronoamperometric testing. The as-prepared Pt1−xCox alloy nanoparticles could be promising cathode catalysts for oxygen reduction in proton exchange membrane fuel cells with the feature of much reduced cost, but significantly increased catalytic activity.

Nanosize carbon-supported Pt1−xCox (x = 0.2, 0.3, and 0.45) electrocatalysts were prepared by a chemical reduction method using sodium borohydride (NaBH4) as the reduction agent. Transmission electron microscopy examination showed uniform dispersion of Pt1−xCox alloy catalysts on carbon matrix, with the particle size less than 10 nm. The electrochemical characteristics of Pt1−xCox alloy catalysts were studied by cyclic voltammetry, linear sweep voltammetry, and chronoamperometric testing. The as-prepared Pt1−xCox alloy nanoparticles could be promising cathode catalysts for oxygen reduction in proton exchange membrane fuel cells with the feature of much reduced cost, but significantly increased catalytic activity.

Ti6Na2O13·nH2O and Ti6Na2O13 nanowires were synthesized by a hydrothermal method. The synthesized Ti6Na2O13 nanowires were used as anode materials for Li-ion cells to examine Li-storage property. The preliminary result shows that this material exhibited a discharge capacity of 1635 mAh/g at first cycle and >1050 mAh/g after second cycle. The Ti6Na2O13 nanowire electrode also showed good property retention upon cycling.

Nanosize carbon-supported Pt1−xCox (x = 0.2, 0.3, and 0.45) electrocatalysts were prepared by a chemical reduction method using sodium borohydride (NaBH4) as the reduction agent. Transmission electron microscopy examination showed uniform dispersion of Pt1−xCox alloy catalysts on carbon matrix, with the particle size less than 10 nm. The electrochemical characteristics of Pt1−xCox alloy catalysts were studied by cyclic voltammetry, linear sweep voltammetry, and chronoamperometric testing. The as-prepared Pt1−xCox alloy nanoparticles could be promising cathode catalysts for oxygen reduction in proton exchange membrane fuel cells with the feature of much reduced cost, but significantly increased catalytic activity.

One-dimensional (1D) SnO2 nanowires were synthesized by a simple heat treatment of Sn–Ag alloys. The presence of Ag in the alloy and a small amount of impurity oxygen in an inert gas played an important role in the growth of SnO2 nanowires. The oxygen content higher than 1 vol.% in the gas resulted in the formation of fine spherical powders. The Li storage property of nano-sized SnO2 for the spherical and 1D SnO2 was evaluated from the lithium intercalation process in a Li-ion cell. The SnO2 nanowires exhibited a better electrochemical performance as an anode than the spherical powders.

In this paper, we present a facile method to synthesize SnO2 nanofibres. Unlike the conventional CVD process for synthesizing nanofibres, the present synthesis method needs neither specific source gas nor substrates. Sn–Ag alloys or powder mixtures were heat-treated at temperatures above their melting point in a vertical or horizontal alumina tube furnace. During the heat treatment, a small amount of oxygen in an atmospheric gas reacted with tin in the alloys to form SnO2 nanofibres. Silver in the tin alloys acts as a catalytic material to facilitate the formation of nanofibres. An excess amount of oxygen in the gas resulted in the formation of SnO2 nanoparticles instead of nanofibres. The synthesized nanofibres have straight form with high purity.

Carbon nanotube/cobalt oxide core-shell one-dimensional nanostructures were prepared via a hydrothermal synthesis method, in which nanosize cobalt oxide crystals were homogeneously coated on the surface of carbon nanotubes. The morphologies and crystal structures of the as-prepared core-shell nanocomposites were analysed by X-ray diffraction, field emission gun scanning electron microscopy, and transmission electron microscopy. When applied as anodes in lithium-ion cells, carbon nanotube/cobalt oxide core-shell nanostructures exhibited an initial lithium storage capacity of 1250 mAh/g and a stable capacity of 530 mAh/g over 100 cycles. The good electrochemical performance could be attributed to the nanocrystalline cobalt oxide and the unique core-shell one-dimensional nanostructures.

One-dimensional (1D) SnO2 nanowires were synthesized by a simple heat treatment of Sn–Ag alloys. The presence of Ag in the alloy and a small amount of impurity oxygen in an inert gas played an important role in the growth of SnO2 nanowires. The oxygen content higher than 1 vol.% in the gas resulted in the formation of fine spherical powders. The Li storage property of nano-sized SnO2 for the spherical and 1D SnO2 was evaluated from the lithium intercalation process in a Li-ion cell. The SnO2 nanowires exhibited a better electrochemical performance as an anode than the spherical powders.

In this paper, we present a facile method to synthesize SnO2 nanofibres. Unlike the conventional CVD process for synthesizing nanofibres, the present synthesis method needs neither specific source gas nor substrates. Sn–Ag alloys or powder mixtures were heat-treated at temperatures above their melting point in a vertical or horizontal alumina tube furnace. During the heat treatment, a small amount of oxygen in an atmospheric gas reacted with tin in the alloys to form SnO2 nanofibres. Silver in the tin alloys acts as a catalytic material to facilitate the formation of nanofibres. An excess amount of oxygen in the gas resulted in the formation of SnO2 nanoparticles instead of nanofibres. The synthesized nanofibres have straight form with high purity.

Carbon nanotube/cobalt oxide core-shell one-dimensional nanostructures were prepared via a hydrothermal synthesis method, in which nanosize cobalt oxide crystals were homogeneously coated on the surface of carbon nanotubes. The morphologies and crystal structures of the as-prepared core-shell nanocomposites were analysed by X-ray diffraction, field emission gun scanning electron microscopy, and transmission electron microscopy. When applied as anodes in lithium-ion cells, carbon nanotube/cobalt oxide core-shell nanostructures exhibited an initial lithium storage capacity of 1250 mAh/g and a stable capacity of 530 mAh/g over 100 cycles. The good electrochemical performance could be attributed to the nanocrystalline cobalt oxide and the unique core-shell one-dimensional nanostructures.

One-dimensional (1D) SnO2 nanowires were synthesized by a simple heat treatment of Sn–Ag alloys. The presence of Ag in the alloy and a small amount of impurity oxygen in an inert gas played an important role in the growth of SnO2 nanowires. The oxygen content higher than 1 vol.% in the gas resulted in the formation of fine spherical powders. The Li storage property of nano-sized SnO2 for the spherical and 1D SnO2 was evaluated from the lithium intercalation process in a Li-ion cell. The SnO2 nanowires exhibited a better electrochemical performance as an anode than the spherical powders.

In this paper, we present a facile method to synthesize SnO2 nanofibres. Unlike the conventional CVD process for synthesizing nanofibres, the present synthesis method needs neither specific source gas nor substrates. Sn–Ag alloys or powder mixtures were heat-treated at temperatures above their melting point in a vertical or horizontal alumina tube furnace. During the heat treatment, a small amount of oxygen in an atmospheric gas reacted with tin in the alloys to form SnO2 nanofibres. Silver in the tin alloys acts as a catalytic material to facilitate the formation of nanofibres. An excess amount of oxygen in the gas resulted in the formation of SnO2 nanoparticles instead of nanofibres. The synthesized nanofibres have straight form with high purity.

Carbon nanotube/cobalt oxide core-shell one-dimensional nanostructures were prepared via a hydrothermal synthesis method, in which nanosize cobalt oxide crystals were homogeneously coated on the surface of carbon nanotubes. The morphologies and crystal structures of the as-prepared core-shell nanocomposites were analysed by X-ray diffraction, field emission gun scanning electron microscopy, and transmission electron microscopy. When applied as anodes in lithium-ion cells, carbon nanotube/cobalt oxide core-shell nanostructures exhibited an initial lithium storage capacity of 1250 mAh/g and a stable capacity of 530 mAh/g over 100 cycles. The good electrochemical performance could be attributed to the nanocrystalline cobalt oxide and the unique core-shell one-dimensional nanostructures.

The feasibility of the infiltration of molten magnesium into porous boron skeleton was examined. The particle size and crystalline state of starting boron powders as well as the confinement of Mg vapors play an important role in successful infiltration. Magnesium penetrates more readily into porous skeletons formed by large crystalline boron particles than those formed by fine amorphous powders. The infiltration of magnesium mainly occurs via capillary condensation rather than liquid flow. Although the infiltrated microstructures are seemingly very dense, nano-scale structures contain many tiny inter-particle voids due to random packing of MgB2 grains. This is due to the absence of a liquid phase in final microstructures as a result of transient liquid-phase infiltration.

The feasibility of the infiltration of molten magnesium into porous boron skeleton was examined. The particle size and crystalline state of starting boron powders as well as the confinement of Mg vapors play an important role in successful infiltration. Magnesium penetrates more readily into porous skeletons formed by large crystalline boron particles than those formed by fine amorphous powders. The infiltration of magnesium mainly occurs via capillary condensation rather than liquid flow. Although the infiltrated microstructures are seemingly very dense, nano-scale structures contain many tiny inter-particle voids due to random packing of MgB2 grains. This is due to the absence of a liquid phase in final microstructures as a result of transient liquid-phase infiltration.

The feasibility of the infiltration of molten magnesium into porous boron skeleton was examined. The particle size and crystalline state of starting boron powders as well as the confinement of Mg vapors play an important role in successful infiltration. Magnesium penetrates more readily into porous skeletons formed by large crystalline boron particles than those formed by fine amorphous powders. The infiltration of magnesium mainly occurs via capillary condensation rather than liquid flow. Although the infiltrated microstructures are seemingly very dense, nano-scale structures contain many tiny inter-particle voids due to random packing of MgB2 grains. This is due to the absence of a liquid phase in final microstructures as a result of transient liquid-phase infiltration.

Field, temperature, and strain dependences of the critical current for a SiC doped multifilamentary in situ MgB2 wire have been studied. Measurement results were compared with that of the undoped wire, and the origin of the difference in the critical current is discussed. The critical current can be calculated with the percolation model considering the effect of anisotropy. The temperature dependence of the fitting parameters, the upper critical field along the ab-plane, and c-axis is compared with the dirty-limit two-gap theory. To assess the validity of the fitting parameters, resistive transition has been measured especially to extract the upper critical field directly. It is shown that even the resistive broadening can be well explained by a simple parallel path model using the fitting parameters obtained from the critical current analysis.

The feasibility of the infiltration of molten magnesium into porous boron skeleton was examined. The particle size and crystalline state of starting boron powders as well as the confinement of Mg vapors play an important role in successful infiltration. Magnesium penetrates more readily into porous skeletons formed by large crystalline boron particles than those formed by fine amorphous powders. The infiltration of magnesium mainly occurs via capillary condensation rather than liquid flow. Although the infiltrated microstructures are seemingly very dense, nano-scale structures contain many tiny inter-particle voids due to random packing of MgB2 grains. This is due to the absence of a liquid phase in final microstructures as a result of transient liquid-phase infiltration.

The feasibility of the infiltration of molten magnesium into porous boron skeleton was examined. The particle size and crystalline state of starting boron powders as well as the confinement of Mg vapors play an important role in successful infiltration. Magnesium penetrates more readily into porous skeletons formed by large crystalline boron particles than those formed by fine amorphous powders. The infiltration of magnesium mainly occurs via capillary condensation rather than liquid flow. Although the infiltrated microstructures are seemingly very dense, nano-scale structures contain many tiny inter-particle voids due to random packing of MgB2 grains. This is due to the absence of a liquid phase in final microstructures as a result of transient liquid-phase infiltration.

In this paper, we present a facile method to synthesize SnO2 nanofibres. Unlike the conventional CVD process for synthesizing nanofibres, the present synthesis method needs neither specific source gas nor substrates. Sn–Ag alloys or powder mixtures were heat-treated at temperatures above their melting point in a vertical or horizontal alumina tube furnace. During the heat treatment, a small amount of oxygen in an atmospheric gas reacted with tin in the alloys to form SnO2 nanofibres. Silver in the tin alloys acts as a catalytic material to facilitate the formation of nanofibres. An excess amount of oxygen in the gas resulted in the formation of SnO2 nanoparticles instead of nanofibres. The synthesized nanofibres have straight form with high purity.

One-dimensional (1D) SnO2 nanowires were synthesized by a simple heat treatment of Sn–Ag alloys. The presence of Ag in the alloy and a small amount of impurity oxygen in an inert gas played an important role in the growth of SnO2 nanowires. The oxygen content higher than 1 vol.% in the gas resulted in the formation of fine spherical powders. The Li storage property of nano-sized SnO2 for the spherical and 1D SnO2 was evaluated from the lithium intercalation process in a Li-ion cell. The SnO2 nanowires exhibited a better electrochemical performance as an anode than the spherical powders.

Field, temperature, and strain dependences of the critical current for a SiC doped multifilamentary in situ MgB2 wire have been studied. Measurement results were compared with that of the undoped wire, and the origin of the difference in the critical current is discussed. The critical current can be calculated with the percolation model considering the effect of anisotropy. The temperature dependence of the fitting parameters, the upper critical field along the ab-plane, and c-axis is compared with the dirty-limit two-gap theory. To assess the validity of the fitting parameters, resistive transition has been measured especially to extract the upper critical field directly. It is shown that even the resistive broadening can be well explained by a simple parallel path model using the fitting parameters obtained from the critical current analysis.

Carbon nanotube/cobalt oxide core-shell one-dimensional nanostructures were prepared via a hydrothermal synthesis method, in which nanosize cobalt oxide crystals were homogeneously coated on the surface of carbon nanotubes. The morphologies and crystal structures of the as-prepared core-shell nanocomposites were analysed by X-ray diffraction, field emission gun scanning electron microscopy, and transmission electron microscopy. When applied as anodes in lithium-ion cells, carbon nanotube/cobalt oxide core-shell nanostructures exhibited an initial lithium storage capacity of 1250 mAh/g and a stable capacity of 530 mAh/g over 100 cycles. The good electrochemical performance could be attributed to the nanocrystalline cobalt oxide and the unique core-shell one-dimensional nanostructures.

beta-Ga2O3 one-dimensional (ID) nanostructures including nanowires, nanoribbons and nanosheets were synthesized via a combined carbon thermal reduction and chemical vapor deposition (CVD) approach. All of these nanostructures consist of single-crystalline monoclinic structure, which has been confirmed via high-resolution TEM and electron diffraction analysis. We obtained beta-Ga2O3 nanowires at high temperature zone, nanosheets, and nanoribbons at medium temperature zone at low-pressure environments. We found that beta-Ga2O3 nanowires and nanoribbons have diversified different growth directions. The optical properties of beta-Ga2O3 nanowires and nanoribbons from UV-vis spectra show that the bandgaps are red-shifted by 0.13 eV.

beta-Ga2O3 one-dimensional (ID) nanostructures including nanowires, nanoribbons and nanosheets were synthesized via a combined carbon thermal reduction and chemical vapor deposition (CVD) approach. All of these nanostructures consist of single-crystalline monoclinic structure, which has been confirmed via high-resolution TEM and electron diffraction analysis. We obtained beta-Ga2O3 nanowires at high temperature zone, nanosheets, and nanoribbons at medium temperature zone at low-pressure environments. We found that beta-Ga2O3 nanowires and nanoribbons have diversified different growth directions. The optical properties of beta-Ga2O3 nanowires and nanoribbons from UV-vis spectra show that the bandgaps are red-shifted by 0.13 eV.

beta-Ga2O3 one-dimensional (ID) nanostructures including nanowires, nanoribbons and nanosheets were synthesized via a combined carbon thermal reduction and chemical vapor deposition (CVD) approach. All of these nanostructures consist of single-crystalline monoclinic structure, which has been confirmed via high-resolution TEM and electron diffraction analysis. We obtained beta-Ga2O3 nanowires at high temperature zone, nanosheets, and nanoribbons at medium temperature zone at low-pressure environments. We found that beta-Ga2O3 nanowires and nanoribbons have diversified different growth directions. The optical properties of beta-Ga2O3 nanowires and nanoribbons from UV-vis spectra show that the bandgaps are red-shifted by 0.13 eV.

beta-Ga2O3 one-dimensional (ID) nanostructures including nanowires, nanoribbons and nanosheets were synthesized via a combined carbon thermal reduction and chemical vapor deposition (CVD) approach. All of these nanostructures consist of single-crystalline monoclinic structure, which has been confirmed via high-resolution TEM and electron diffraction analysis. We obtained beta-Ga2O3 nanowires at high temperature zone, nanosheets, and nanoribbons at medium temperature zone at low-pressure environments. We found that beta-Ga2O3 nanowires and nanoribbons have diversified different growth directions. The optical properties of beta-Ga2O3 nanowires and nanoribbons from UV-vis spectra show that the bandgaps are red-shifted by 0.13 eV.