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Diamond has become a promising candidate for high-power devices based on its ultrawide bandgap and excellent thermoelectric properties, where an appropriate gate dielectric has been a bottleneck hindering the development of diamond devices. Herein, we have systematically investigated the structural arrangement and electronic properties of diamond/high-κ oxide (HfO 2 , ZrO 2 ) heterojunctions by first-principles calculations with a SiO 2 interlayer. Charge analysis reveals that the C-Si bonding interface attracts a large amount of charge concentrated at the diamond interface, indicating the potential for the formation of a 2D hole gas (2DHG). The diamond/HfO 2 and diamond/ZrO 2 heterostructures exhibit similar "Type II" band alignments with VBOs of 2.47 and 2.21 eV, respectively, which is consistent with experimental predictions. The introduction of a SiO 2 dielectric layer into the diamond/SiO 2 /high-κ stacks exhibits the typical "Type I″ straddling band offsets (BOs). In addition, the wide bandgap SiO 2 interlayer keeps the valence band maximum (VBM) and conduction band minimum (CBM) in the stacks away from those of diamond, effectively confining the electrons and holes in MOS devices. This work exhibits the potential of SiO 2 /high-κ oxide gate dielectrics for diamond devices and provides theoretical insights into the rational design of high-quality gate dielectrics for diamond-based MOS device applications.

This paper thoroughly analyses the role of drift in the sensitive region in the single-event effect (SEE), with the aim of enhancing the single-particle radiation resistance of N-type metal-oxide semiconductor field-effect transistors (MOSFETs). It proposes a design for a Si-based device structure that extends the lightly doped source-drain region of the N-channel metal-oxide semiconductor (NMOS), thereby moderating the electric field of the sensitive region. This design leads to a 15.69% decrease in the charge collected at the leaky end of the device under the standard irradiation conditions. On this basis, a device structure is further proposed to form a composite metal-oxide semiconductor (MOS) by connecting a pn junction at the lightly doped source-drain end. By adding two charge paths, the leakage collection charge is further reduced by 13.85% under standard irradiation conditions. Moreover, the deterioration of the drive current in the purely growing lightly doped source-drain region can be further improved. Simulations of single-event effects under different irradiation conditions show that the device has good resistance to single-event irradiation, and the composite MOS structure smoothly converges to a 14.65% reduction in drain collection charge between 0.2 pC/μm and 1 pC/μm Linear Energy Transfer (LET) values. The incidence position at the source-to-channel interface collects the highest charge reduction rate of 28.23%. The collecting charge reduction rate is maximum, at 17.12%, when the incidence is at a 45-degree angle towards the source.

In this paper, the transient breakdown voltage ( TrBV ) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage ( BV lat ). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region ( N d ) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration ( P sub ) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage ( BV ver ) and suppressed an increase in the specific on-resistance ( R on,sp ). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower R on,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time ( T nonbv ) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, R on,sp was 37.74% lower, and T nonbv was 10% longer than those of the double RESURF SOI LDMOS.

Breathing poor-quality air is a global threat at the same level as unhealthy diets or tobacco smoking, so the availability of affordable instrument for the measurement of air pollutant levels is highly relevant for human and environmental protection. We developed an air quality monitoring platform that comprises a wearable device embedding low-cost metal oxide semiconductor (MOS) gas sensors, a PM sensor, and a smartphone for collecting the data using Bluetooth Low Energy (BLE) communication. Our own developed app displays information about the air surrounding the user and sends the gathered geolocalized data to a cloud, where the users can map the air quality levels measured in the network. The resulting device is small-sized, light-weighted, compact, and belt-worn, with a user-friendly interface and a low cost. The data collected by the sensor array are validated in two experimental setups, first in laboratory-controlled conditions and then against referential pollutant concentrations measured by standard instruments in an outdoor environment. The performance of our air quality platform was tested in a field testing campaign in Barcelona with six moving devices acting as wireless sensor nodes. Devices were trained by means of machine learning algorithms to differentiate between air quality index (AQI) referential concentration values (97% success in the laboratory, 82.3% success in the field). Humidity correction was applied to all data., Competing Interests: Declaration of competing interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper., (Copyright © 2022 Elsevier Ltd. All rights reserved.)

For some years now, the ever continuing dimensional scaling has no longer been considered to be sufficient for the realization of advanced CMOS devices. Alternative approaches, such as employing new materials and introducing new device architectures, appear to be the way to go forward. A currently hot approach is to employ ferroelectric materials for obtaining a positive feedback in the gate control of a switch. This work elaborates on two device architectures based on this approach: the negative-capacitance and the piezoelectric field-effect transistor, i.e., the NC-FET (negative-capacitance field-effect transistor), respectively π -FET. It briefly describes their operation principle and compares those based on earlier reports. For optimal performance, the adopted ferroelectric material in the NC-FET should have a relatively wide polarization-field loop (i.e., "hard" ferroelectric material). Its optimal remnant polarization depends on the NC-FET architecture, although there is some consensus in having a low value for that (e.g., HZO (Hafnium-Zirconate)). π -FET is the piezoelectric coefficient, hence its polarization-field loop should be as high as possible (e.g., PZT (lead-zirconate-titanate)). In summary, literature reports indicate that the NC-FET shows better performance in terms of subthreshold swing and on-current. However, since its operation principle is based on a relatively large change in polarization the maximum speed, unlike in a π -FET, forms a big issue. Therefore, for future low-power CMOS, a hybrid solution is proposed comprising both device architectures on a chip where hard ferroelectric materials with a high piezocoefficient are used.

We report a new technique for the rapid measurement of full capacitance-voltage (C-V) characteristic curves. The displacement current from a 100 MHz applied sine-wave, which swings from accumulation to strong inversion, is digitized directly using an oscilloscope from the metal-oxide-semiconductor (MOS) capacitor under test. A C-V curve can be constructed directly from this data but is severely distorted due to non-ideal behavior of real measurement systems. The key advance of this work is to extract the system response function using the same measurement set-up and a known MOS capacitor. The system response correction to the measured C-V curve of the unknown MOS capacitor can then be done by simple deconvolution. No de-skewing and/or leakage current correction is necessary, making it a very simple and quick measurement. Excellent agreement between the new fast C-V method and C-V measured conventionally by an LCR meter is achieved. The total time required for measurement and analysis is approximately 2 seconds, which is limited by our equipment.