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This paper presents a multicasting solution for shared-buffer ATM switch. The cell duplicating function is performed by a one-to-many modified demux circuit. A shared multicast server is used to translate input multicast cells to find destination ports and corresponding routing information. By using link-list based ring structure, the multicast server can provide high speed (5 ns to search entry in 256-entry block in 0.8-[[micro]meter] CMOS process) and cascadable multicast translating function. In addition, the channel complexity of multipoint-to-multipoint multicast applications can be reduced to N channels per N users. The shared-buffer controller is modified by adding controlling and scheduling functions for multicasting queues to process the multicast feature. Finally with the aid of the quality of service (QoS) management, this proposed solution provides multi-QoS for multicast cells to meet the needs of various video applications. Index Terms - ATM switch, communication system, multicast cells, quality of service, VLSI architecture.

This paper presents a very efficient VLSI architecture for real-time median filtering as requested in many image/video applications. The median is obtained by first sorting input sequences and then selecting identified order according to the number of inputs. To reach the goal of high-speed data sorting, an optimized delete-and-insert algorithm is derived and then mapped onto shiftable content-addressable memory architecture. The complete design can be decomposed into a set of processor elements, where each processor element consists of two basic cells - sort-cell and compare-cell. Thus the design becomes very regular. More specifically any specified order can be obtained within one cycle and a high-speed clock rate can be achieved. A proto-type chip for 64 samples based on this architecture has been implemented and tested. Results show that a clock rate up to 50 MHz can be achieved using a 1.2 [[micro]meter] CMOS double metal technology.