Search

An architecture of densely connected compact neural networks is presented for the maximum-likelihood sequence estimation (MLSE) of signals in digital communications. The combinatorial minimization of the detection cost is performed through the optimization of a concave Laypunov function associated with the network, and truly paralleled operations can be achieved via the collective computational behaviors. In addition, the MLSE performance can be improved by a paralleled annealing technique which has been developed for obtaining optimal or near-optimal solutions in high-speed, real-time applications. Given a sequence of length n, the network of complexity and throughput rate are O(L) and n/[T.sub.c], respectively, where L is the number of symbols the inference spans and [T.sub.c] is the convergence time. The hardware architecture as well as network models, neuron models, and methods of feeding the input to the network are addressed in terms of the probability of error. Through the simulations, it is demonstrated that the proposed compact neural network approach is an efficient method of realizing the MLSE receiver.

An engineering annealing method, called hardware annealing method, for optimal solutions on cellular neural networks is presented. Cellular neural networks have great potential in solving many important scientific problems in signal processing and optimization by use of pre-determined templates. Hardware annealing, which is a parallel version of effective mean-field annealing in analog networks, is a highly efficient method to find optimal solutions on cellular neural networks. It does not require any iterative stochastic procedure and henceforth can be very fast. The landscape of the network energy function is first adapted so that the whole annealing process does not get stuck at a local minimum at the beginning of searching for optimal solutions by adjusting each neuron to a low voltage gain. Then, the hardware annealing searches for the globally minimum energy state by continuously increasing the gain of neurons. The globally optimal equilibrium state is reached when each neuron is at its maximum voltage gain. The robustness of this proposed hardware annealing method for global optimization is assessed by analysis of the eigenvalues in a corresponding dynamical system model.

An engineering annealing method for optimal solutions of cellular neural networks is presented. Cellular neural networks are very promising in solving many scientific problems in image processing, pattern recognition, and optimization by the use of stored program with predetermined templates. Hardware annealing, which is a paralleled version of mean-field annealing in analog networks, is a highly efficient method of finding optimal solutions of cellular neural networks. It does not require any stochastic procedure and henceforth can be very fast. The generalized energy function of the network is first increased by reducing the voltage gain of each neuron. Then, the hardware annealing searches for the globally minimum energy state by continuously increasing the gain of neurons. The process of global optimization by the proposed annealing can be described by the eigenvalue problems in the time-varying dynamic system. In typical nonoptimization problems, it also provides enough stimulation to frozen neurons caused by ill-conditioned initial states.

A 3 V CMOS VLSI for dual-mode wireless communication systems has been designed and fabricated using the MOSIS scaleable CMOS technology. By using mixed analog and digital circuit design techniques, a single chip solution to baseband processing of data and supervisory audio tone signals in the analog transmission mode is possible. Key analog circuits include an anti-alias filter, two fifth-order low-pass filters, one sixth-order band-pass filter, an interpolator for sampling rate conversion, and two comparators. The digital modules perform data transmission and reception, error coding and decoding, as well as tone detection and regeneration. When implemented in the 2 [[micro]meter] CMOS technology from the MOSIS Service for low-cost low-power applications, the transceiver chip consumes less than 6 mW at receive-only mode. It is also quite suitable for battery-powered devices, such as portable terminals. Design technologies can be applied to future high-speed wireless transceiver design. The architecture and circuits described in this chip can be used in aggressively scaled technologies even with the supply voltage reduced toward 1 V if the threshold voltage is proportionally decreased.

An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require a priori estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mm X 6.8 mm and was fabricated in a 2-micrometer double-polysilicon CMOS technology. System analysis and experimental result are presented.