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The emergence of blockchain technology, characterized by its immutable and decentralized digital ledger system, has sparked significant interest due to its potential to revolutionize several industries. Simultaneously, Long-Term Evolution (LTE) networks have emerged as the fundamental infrastructure for facilitating high-speed wireless communication. The correlation between these two technologies is still a subject that has yet to be well studied despite its potential significance for addressing the scalability issues of blockchain. The article aimed to explore the possible advantages and improvements that might arise from integrating Long-Term Evolution (LTE) networks into blockchain systems, with a specific emphasis on scalability, reliability, and efficiency. This study introduced a unique framework, incorporating Long-Term Evolution (LTE) as a supplementary communication layer to enhance the current Peer-to-Peer (P2P) blockchain architecture. The comprehensive studies included powerful simulation models, practical testing, and comparison analysis against widely used scaling options such as Layer 2 protocols and sharding. Results: The experimental findings indicate that integrating LTE technology with blockchain resulted in a substantial increase in transaction throughput and a noteworthy decrease in confirmation times. Significantly, this innovation did not compromise the inherent decentralized character of the blockchain. Moreover, the LTE-augmented blockchain exhibits a higher resilience level than conventional blockchain systems when faced with common network risks, like Sybil and Eclipse assaults. Long-Term Evolution (LTE) networks in blockchain systems create a collaborative telecom-blockchain framework. This combination could benefit banking, supply chain management, and the Internet of Things. The findings show that LTE networks help blockchain technology scale and survive.

In recent years, advancements in telecommunication technology have led to the proliferation of high-speed, large-capacity, low-latency communication. The COVID-19 pandemic has also accelerated the adoption of remote work globally, making real-time remote communication applications like web conferencing crucial for business, education, and other sectors. Despite the various demands for streaming applications, existing services often fail to meet the requirements of scenarios demanding ultra-low latency, such as surgical operations, remote control of automobiles, and real-time collaborative performances. To address this, we explored using FPGAs to achieve ultra-low latency processing in image processing tasks, explicitly focusing on background removal. Our study demonstrated the feasibility of using commercially available FPGA devices to reduce latency in background subtraction significantly compared to conventional methods. The results indicate that FPGA-based processing can provide the ultra-low latency needed for critical applications, enhancing the performance and user experience in remote operations and real-time streaming.

The demand for ultra-reliable low-latency communications (URLLC) has led to the adoption of grant-free (GF) access techniques by the 5G NR, with the goal of reducing uplink access time. When GF access is employed, the base station (BS) preallocates multiple transmission opportunities (TOs) that can be utilized by the user equipment (UE) as needed. However, this approach results in inefficient resource utilization as unused TOs are wasted. To overcome this inefficiency, the 5G NR allows the assignment of configured grants (CG) to a group of UEs instead of a single one. This development has led research into group-based CG (GCG) schemes, whose reliance on shared resources can result in collisions. The collisions can be prevented by the use of stop-and-wait IR-HARQ schemes. Nevertheless, the delay caused by feedback latency is also undesirable as it severely affects latency performance. This work proposes two new IR-HARQ GCG schemes to efficiently handle feedback latency. The first one is able to eliminate the feedback latency overhead and is proven to simultaneously achieve the latency of a one-shot transmission and the energy efficiency of IR-HARQ, even in the presence of non-instantaneous feedback signaling. The second one features both a feedback latency protection mechanism, similar to the first scheme, and a mechanism specifically designed to further reduce latency. The performance of the proposed schemes is compared with scenarios where each UE uses either an individual one-shot or an IR-HARQ scheme. These comparisons encompass scenarios with either power or energy constraints. The results have shown that the second scheme always outperforms the IR-HARQ scheme and that it is able to outperform the one-shot scheme on a wide interval of feedback latency values, achieving a lower latency both for power and energy constrained cases.

To achieve low-latency and energy-efficient in a 10 Gbps Ethernet Passive Optical Network (10G-EPON) having heterogeneous Optical Network Unit (ONU) propagation delays, this article proposes a resource allocation scheme based on bandwidth requirements prediction and ONU polling sequence scheduling. By a) predicting the upstream (US) and downstream (DS) bandwidth requirements of each ONU using Long Short-Term Memory (LSTM) networks and b) arranging the ONU polling sequence and the US and DS transmission start times of each ONU based on the predicted bandwidth requirements and the ONU propagation delays, the proposed scheme minimizes bandwidth waste of the network as well as the overall operating time of each ONU. Therefore, low-latency performance is achieved, and the energy consumption of ONUs is reduced as ONU sleeping time is extended. Simulation results indicate that the proposed scheme reduces network latency and improves energy efficiency effectively. Compared to the conventional Interleaved Polling with Adaptive Cycle Time scheme that adopts the shortest propagation delay first rule and ONU doze mode, the proposed scheme can reduce the average one-way packet delay by at least 28.9%, and can reduce the per bit energy consumption by 73.7% when concerning data transmitted under the 1 ms latency constraint.

Cloud gaming allows users to play high-quality games on low-end devices by offloading game processing to the cloud. However, network latency remains a significant issue affecting the gaming experience. Speculative execution is a promising approach to hide network latency by predicting and transmitting future frames early. However, existing methods generate excessive compute load and network traffic due to many potential input patterns. This paper introduces a pattern reduction method that uses a bit field representation of the input and facilitates efficient speculative execution in cloud games. There are two pattern reduction techniques: analyzing temporal patterns to detect frequent transitions and using LSTM-based predictions to estimate input probabilities. Experiments using actual gaming data show that the proposed methods significantly reduce rendered frames and network traffic versus prior speculative execution methods. The results demonstrate the method’s effectiveness and scalability across diverse game genres.

In this article, we introduce a causal low-latency low-complexity approach for binaural multichannel blind speaker separation in noisy reverberant conditions. The model, referred to as Group Communication Binaural Filter and Sum Network (GCBFSnet) predicts complex filters for filter-and-sum beamforming in the time-frequency domain. We apply Group Communication (GC), i.e., latent model variables are split into groups and processed with a shared sequence model with the aim of reducing the complexity of a simple model only containing one convolutional and one recurrent module. With GC we are able to reduce the size of the model by up to 83% and the complexity up to 73% compared to the model without GC, while mostly retaining performance. Even for the smallest model configuration, GCBFSnet matches the performance of a low-complexity TasNet baseline in most metrics despite the larger size and higher number of required operations of the baseline.

A tone mapping operator (TMO) is a module in the image signal processing pipeline that is used to convert high dynamic range images to low dynamic range images for display. Currently, state-of-the-art TMOs typically take complex algorithms and are implemented on graphics processing units, making it difficult to run with low latency on edge devices, and TMOs implemented in hardware circuits often lack additional noise suppression because of latency and hardware resource constraints. To address these issues, we proposed a low-latency noise-aware TMO for hardware implementation. Firstly, a locally weighted guided filter is proposed to decompose the luminance image into a base layer and a detail layer, with the weight function symmetric concerning the central pixel value of a window. Secondly, the mean and standard deviation of the basic layer and the detail layer are used to estimate the noise visibility according to the human visual characteristics. Finally, the gain for the detail layer is calculated to achieve adaptive noise suppression. In this process, luminance is first processed by the log2 function before being filtered and then symmetrically converted back to the linear domain by the exp2 function after compression. Meanwhile, the algorithms within the proposed TMO were optimized for hardware implementation to minimize latency and cache, achieving a low latency of 60.32 μs under video specification of 1080 P at 60 frames per second and objective metric smoothness in dark flat regions could be improved by more than 10% compared to similar methods.

The increase in popularity of wireless networks in industrial, embedded, medical and public sectors has made them an appealing attack surface for attackers who exploit the vulnerabilities in network protocols to launch attacks such as Evil Twin, Man-in-the-middle, sniffing, etc., which may result in economic and non-economic losses. To protect wireless networks against such attacks, IEEE 802.11 keep updating the protocol standards with new and more secure versions. There has always been a direct correlation between attacks and the improvement of protocol standards. As the sophistication of attacks increases, protocol standards tend to move towards higher security, resulting in a significant rise in both latency and computational overhead, and severe degradation in the performance of low-latency applications such as Industrial Internet of Things (IIoT), automotive, robotics, etc. In this paper, we make an attempt to highlight the importance of both latency and security in wireless networks from implementation and performance perspective. We make a review of existing IEEE 802.11 protocols in terms of security offered and overhead incurred to substantiate the fact that there is a need of a protocol which in addition to providing optimum security against attacks also maintains the latency and overhead. We also propose a secure and low-latency protocol known as Secure Authentication Protocol (SAP) which operates in two phases - registration and authentication, where the first phase is a one time process implemented using asymmetric cryptography and the second phase is implemented using symmetric cryptography. The protocol is structured in a way that it maintains the original structure of IEEE 802.11 protocols and performs both phases using fewer messages than existing protocols. By simulating the protocol using well-established OMNeT++ simulator, we proved that the proposed protocol incurs a low computation overhead, making it ideal for low-latency applications. We extensively verified the security properties of the proposed protocol using formal verification through widely-accepted Scyther tool. Finally, we perform a comparative analysis of SAP with existing IEEE 802.11 wireless network protocols to highlight the improvement.

The automotive Ethernet is an emerging area for exploiting the high network bandwidth and scalable network design in automated driving systems. Low-latency live video streaming over the automotive Ethernet is a challenging part of this concept because of its significance for driving situation awareness in real time. In order to achieve low-latency live video streaming on resource-constrained automotive electric control units, the streaming needs to be conducted with a fine-grained resource control. This article proposes a raw format live video streaming framework that resiliently controls the number of raw format video packets with consideration of available CPU resources. The evaluation on a testbed demonstrates that the proposed framework achieves low-latency live video streaming by securing available CPU resources.

The ultra-reliable low-latency communications (URLLC) tight latency requirements paired with transmission of small payload packets motivates the development of techniques that reduce or eliminate the need for dynamic scheduling. This justifies the study of grant free (GF) leveraged techniques in order to reduce both the latency and control signaling overhead. Previous works considered preallocating resources not only for the first transmission, but also for all possible IR-HARQ transmissions, effectively reducing the scheduling latency and control signaling overhead. However, this has several drawbacks, as it translates into wasted resources. To address these issues, we propose a group-based preallocation method combined with IR-HARQ. Initially, a pool of preallocated resources is assigned to a group of users, which then cooperatively use IR-HARQ feedback signals to distribute, on the fly, the resources amongst them without collisions. The proposed method has two phases: a preallocation phase that takes place once at the group formation stage and a transmission phase which happens at each uplink transmission. The transmission parameters for all possible transmission scenarios are selected at the preallocation stage, with the goal of reducing the latency under reliability and energy constraints. The transmission parameters are obtained through a constrained latency optimization procedure, which considers the stochastic nature of the underlying process. We prove that, asymptotically, the proposed scheme is able to reduce the latency, at least, down to the average latency of any single user (SU) HARQ. The numerical results show that the latency and resources wastage is significantly reduced comparatively to single user IR-HARQ with preallocated resources.

Live media streaming is a challenging task by itself, and when it comes to use cases that define low-latency as a must, the complexity will rise multiple times. In a typical media streaming session, the main goal can be declared as providing the highest possible Quality of Experience (QoE), which has proved to be measurable using quality models and various metrics. In a low-latency media streaming session, the requirements are to provide the lowest possible delay between the moment a frame of video is captured and the moment that the captured frame is rendered on the client screen, also known as end-to-end (E2E) latency and maintain the QoE. This paper proposes a sophisticated cloud-based and open-source testbed that facilitates evaluating a low-latency live streaming session as the primary contribution. Live Low-Latency Cloud-based Adaptive Video Streaming Evaluation (LLL-CAdViSE) framework is enabled to asses the live streaming systems running on two major HTTP Adaptive Streaming (HAS) formats, Dynamic Adaptive Streaming over HTTP (MPEG-DASH) and HTTP Live Streaming (HLS). We use Chunked Transfer Encoding (CTE) to deliver Common Media Application Format (CMAF) chunks to the media players. Our testbed generates the test content (audiovisual streams). Therefore, no test sequence is required, and the encoding parameters (e.g., encoder, bitrate, resolution, latency) are defined separately for each experiment. We have integrated the ITU-T P.1203 quality model inside our testbed. To demonstrate the flexibility and power of LLL-CAdViSE, we have presented a secondary contribution in this paper; we have conducted a set of experiments with different network traces, media players, ABR algorithms, and with various requirements (e.g., E2E latency (typical/reduced/low/ultra-low), diverse bitrate ladders, and catch-up logic) and presented the essential findings and the experimental results.

The entire world progression has ceased with the unexpected outbreak of the COVID-19 pandemic, and urges the requirement for contact-less and autonomous services and applications. Realizing these predominantly Internet of Things (IoT) based applications demands a holistic pervasive computing infrastructure. In this paper, we conduct a survey to determine the possible pervasive approaches for utilizing the Multi-Access Edge Computing (MEC) infrastructure in realizing the requirements of emerging IoT applications. We have formalized specific architectural layouts for the considered IoT applications, while specifying network-level requirements to realize such approaches; and conducted a simulation to test the feasibility of proposed MEC approaches.

The recent surge in human-controlled robotics and haptic devices research is expediting a paradigm shift in today’s communication networks towards human-to-robot (H2R) centric technologies that support Industrial Internet of Things (IIoT) and Industry 5.0. In both IIoT and Industry 5.0, human skills are extended through collaboration with robots that are geographically separated from the human. Depending on the dynamicity of the actual use case, human-to-robot communications necessitate low-latency networking. While Long Term Evolution (LTE) cellular technology has been successful in fulfilling the bandwidth demands of massively-connected sensors and devices of Industry 4.0, it is insufficient to meet the low latency demands of the future Industry 5.0 where dynamic interactions between humans and robots are paramount. In reducing the latency caused by radio resource contention in wireless H2R communications, in this work, we propose a novel approach that exploits an Attention-based Recurrent Neural Network (Att-RNN) to improve the Semi-Persistent Scheduling (SPS) resource allocation scheme adopted by LTE and new radio (NR) standards developed for the fifth generation (5G) mobile networks. We conduct a series of real haptic experiments to collect H2R traffic traces to train, test and evaluate the accuracy of Att-RNN in predicting H2R traffic. Then, with extensive simulations based on the empirical H2R traffic traces, we show that our proposed Att-RNN SPS scheme outperforms classic SPS and other existing resource allocation schemes in terms of reduced latency and improved resource allocation efficiency, thus making Att-RNN SPS a suitable candidate in future Industry 5.0 deployments.

Highly immersive content in the form of extended reality (XR) is attracting attention as an alternative to conventional video services such as YouTube and Facebook. Many galleries and museums already offer online virtual reality (VR) tours where users are free to choose the spot they want to move to, beyond merely looking around. Although the ease of implementation, this key-spot hopping is still far from giving the real feeling of walking. Meanwhile, in recent volumetric or light-field-based studies, view rendering that supports free and continuous viewpoint movements has been attempted. With online services in mind, however, the high data volume and computational complexity are a big obstacle to practical applications. Path-walking VR, the target system of this paper, can be a good compromise, where the viewer can enjoy the virtual space while walking along the route. The interactive path-walking VR service is entry-level immersive video, but streaming over the network is still challenging. One of the main problems to be tackled is that the movement patterns of viewers need to be reflected in the streaming strategy to improve the quality of experience. Unlike unidirectional video, the movement of the viewer determines which images and how many images should be transmitted. This paper proposes schemes to reduce streaming delays by reflecting the viewer’s movement characteristics. It is differentiated from existing studies for omnidirectional video in that the proposed schemes control not only image quality but also view update rate. The first is a caching strategy which takes advantage of the geometrical locality of the virtual space that the viewer will soon reach a position close to the current position. This not only reduces the communication delay from the server, but also decreases the burden of server-side request handling. The second scheme uses the relationship between the viewer’s speed and the field of vision. The image quality is adjusted according to the viewer’s speed and head direction. Experimental results show that the proposed schemes achieve stable viewer’s experience by considering walking characteristics in virtual space. It is expected that the results of this paper will provide insight to those who design interactive streaming systems for immersive media applications.

A verifiable delay function (VDF) is a function whose evaluation requires running a prescribed number of sequential steps over a group while the result can be efficiently verified. As a kind of cryptographic primitives, VDFs have been adopted in rapidly growing applications for decentralized systems. For the security of VDFs in practical applications, it is widely agreed that the fastest implementation for the VDF evaluation, sequential squarings in a group of unknown order, should be publicly provided. To this end, we propose a possible minimum latency hardware implementation for the squaring in class groups by algorithmic and architectural level co-optimization. Firstly, low-latency architectures for large-number division, multiplication, and addition are devised using redundant representation, respectively. Secondly, we present two hardware-friendly algorithms which avoid time-consuming divisions involved in calculations related to the extended greatest common divisor (XGCD) and design the corresponding low-latency architectures. Besides, we schedule and reuse these computation modules to achieve good resource utilization by using compact instruction control. Finally, we code and synthesize the proposed design under the TSMC 28nm CMOS technology. The experimental results show that our design can achieve a speedup of 3.6x compared to the state-of-the-art implementation of the squaring in the class group. Moreover, compared to the optimal C++ implementation over an advanced CPU, our implementation is 9.1x faster.

Recently, a memory safety concept called Cryptographic Capability Computing (C3) has been proposed. C3 is the first memory safety mechanism that works without requiring extra storage for metadata and hence, has the potential to significantly enhance the security of modern IT-systems at a rather low cost. To achieve this, C3 heavily relies on ultra-low-latency cryptographic primitives. However, the most crucial primitive required by C3 demands uncommon dimensions. To partially encrypt 64-bit pointers, a 24-bit tweakable block cipher with a 40-bit tweak is needed. The research on low-latency tweakable block ciphers with such small dimensions is not very mature. Therefore, designing such a cipher provides a great research challenge, which we take on with this paper. As a result, we present BipBip, a 24-bit tweakable block cipher with a 40-bit tweak that allows for ASIC implementations with a latency of 3 cycles at a 4.5 GHz clock frequency on a modern 10 nm CMOS technology.

In this paper, we study the gate depth complexity of (vectorial) Boolean functions in the basis of {NAND, NOR, INV} as a new metric, called latency complexity, to mathematically measure the latency of Boolean functions. We present efficient algorithms to find all Boolean functions with low-latency complexity, or to determine the latency complexity of the (vectorial) Boolean functions, and to find all the circuits with the minimum latency complexity for a given Boolean function. Then, we present another algorithm to build bijective S-boxes with low-latency complexity which with respect to the computation cost, this algorithm overcomes the previous methods of building S-boxes. As a result, for latency complexity 3, we present n-bit S-boxes of 3 ≤ n ≤ 8 with linearity 2n−1 and uniformity 2n−2 (except for 5-bit S-boxes for whose the minimum achievable uniformity is 6). Besides, for latency complexity 4, we present several n-bit S-boxes of 5 ≤ n < 8 with linearity 2n−2 and uniformity 2n−4.

Research on the design of masked cryptographic hardware circuits in the past has mostly focused on reducing area and randomness requirements. However, many embedded devices like smart cards and IoT nodes also need to meet certain performance criteria, which is why the latency of masked hardware circuits also represents an important metric for many practical applications. The root cause of latency in masked hardware circuits is the need for additional register stages that synchronize the propagation of shares. Otherwise, glitches would violate the basic assumptions of the used masking scheme. This issue can be addressed to some extent, e.g., by using lightweight cryptographic algorithms with low-degree Sboxes, however, many applications still require the usage of schemes with higher-degree S-boxes like AES. Several recent works have already proposed solutions that help reduce this latency yet they either come with noticeably increased area/randomness requirements, limitations on masking orders, or specific assumptions on the general architecture of the crypto core. In this work, we introduce a generic and efficient method for designing single-cycle glitch-resistant (higher-order) masked hardware of cryptographic S-boxes. We refer to this technique as (generic) Self-Synchronized Masking (“SESYM”). The main idea of our approach is to replace register stages with a partial dual-rail encoding of masked signals that ensures synchronization within the circuit. More concretely, we show that WDDL gates and Muller C-elements can be used in combination with standard masking schemes to design single-cycle S-box circuits that, especially in case of higher-degree S-boxes, have noticeably lower requirements in terms of area and online randomness. We apply our method to DOM-based S-boxes of Ascon and AES and compare the resulting circuits to existing latency optimized circuits based on TI, GLM, and LMDPL. The latency of all three designs is reduced to single-cycle operation and are dth-order secure. Compared to GLM-masked Ascon, our approach comes with a 6.4 times reduction in online randomness for all protection orders. Compared to 1st-order LMDPL-masked AES, our approach achieves comparable results, while it is more generic, amongst others, by also supporting higher-order designs. We also underline the practical protection of our constructions against power analysis attacks via empirical and formal verification approaches.

Research on the design of masked cryptographic hardware circuits in the past has mostly focused on reducing area and randomness requirements. However, many embedded devices like smart cards and IoT nodes also need to meet certain performance criteria, which is why the latency of masked hardware circuits also represents an important metric for many practical applications. The root cause of latency in masked hardware circuits is the need for additional register stages that synchronize the propagation of shares. Otherwise, glitches would violate the basic assumptions of the used masking scheme. This issue can be addressed to some extent, e.g., by using lightweight cryptographic algorithms with low-degree Sboxes, however, many applications still require the usage of schemes with higher-degree S-boxes like AES. Several recent works have already proposed solutions that help reduce this latency yet they either come with noticeably increased area/randomness requirements, limitations on masking orders, or specific assumptions on the general architecture of the crypto core. In this work, we introduce a generic and efficient method for designing single-cycle glitch-resistant (higher-order) masked hardware of cryptographic S-boxes. We refer to this technique as (generic) Self-Synchronized Masking (“SESYM”). The main idea of our approach is to replace register stages with a partial dual-rail encoding of masked signals that ensures synchronization within the circuit. More concretely, we show that WDDL gates and Muller C-elements can be used in combination with standard masking schemes to design single-cycle S-box circuits that, especially in case of higher-degree S-boxes, have noticeably lower requirements in terms of area and online randomness. We apply our method to DOM-based S-boxes of Ascon and AES and compare the resulting circuits to existing latency optimized circuits based on TI, GLM, and LMDPL. The latency of all three designs is reduced to single-cycle operation and are dth-order secure. Compared to GLM-masked Ascon, our approach comes with a 6.4 times reduction in online randomness for all protection orders. Compared to 1st-order LMDPL-masked AES, our approach achieves comparable results, while it is more generic, amongst others, by also supporting higher-order designs. We also underline the practical protection of our constructions against power analysis attacks via empirical and formal verification approaches.

Integrated energy service is the main form of future energy supply. Integrated energy optimization and integration can make full use of distributed energy and renewable energy. In this paper, a set of low-latency integrated energy conversion equipment with electricity as the core have been designed to meet the comprehensive energy requirements of electricity, cooling, heating, hot water, etc. The distributed photovoltaic power generation, micro-turbine combined heat and power, electrochemical energy storage, hot water storage tanks, electric auxiliary heat, ground source heat pumps and multi-port power converter were integrated with low-latency fast local communication to achieve the coordinated control between energy portfolios. And with the lowest operating cost, maximum renewable energy utilization, and highest energy utilization efficiency as the control objects, uses power electronics converter millisecond-level high-speed response performance and inertia controllability, to support the conversion of single energy flow to multi-energy flow, ensure the reliable, economical, efficient and green operation of the user’s integrated energy system, realize multi-energy complementation, and energy cascade utilization.

Short-reach transmission systems traditionally utilize intensity modulation (IM) at the transmitter and direct detection (DD) at the receiver due to their cost-effectiveness, small footprint, and low power consumption. However, with the exponential increase in bandwidth demand, coherent optical communication systems have become necessary for long-haul distances, requiring application-specific integrated circuits (ASIC) and advanced digital signal processing (DSP) algorithms coupled with high-speed digital-to-analog and analog-to-digital converters to achieve Tbit/s speeds. As coherent technology matures, it will eventually become feasible for short-reach transmission. In this context, self-coherent systems have emerged as an intermediary solution, offering advantages over traditional IM/DD systems. While comprehensive review studies exist on self-coherent transceivers, they do not cover recent advances in phase retrieval methods for short-reach optical communications. This review article highlights recent developments in cost-effective self-coherent detection for short-reach systems through comparing the benefits of single sideband (SSB) transmission and Kramers-Kronig detection to carrier-assisted phase retrieval, the Gerchberg-Saxton (GS) algorithm, and the transport of intensity equation (TIE) method.

The 3rd Generation Partnership Project (3GPP) is investing a notable effort to mitigate the endogenous stack and protocol delays (e.g., introducing new numerology, through preemptive scheduling or providing uplink granted free transmission) to attain to the heterogeneous Quality of Service (QoS) latency requirements for which the fifth generation technology standard for broadband cellular networks (5G) is envisioned. However, 3GPP’s goals may become futile if exogenous delays generated by the transport layer (e.g., bufferbloat) and the Radio Link Control (RLC) sublayer segmentation/reassembly procedure are not targeted. On the one hand, the bufferbloat specifically occurs at the Radio Access Network (RAN) since the data path bottleneck is located at the radio link, and contemporary RANs are deployed with large buffers to avoid squandering scarce wireless resources. On the other hand, a Resource Block (RB) scheduling that dismisses 5G’s packet-switched network nature, unnecessarily triggers the segmentation procedure at sender’s RLC sublayer, which adds extra delay as receiver’s RLC sublayer cannot forward the packets to higher sublayers until they are reassembled. Consequently, the exogenously generated queuing delays can surpass 5G’s stack and protocol endogenous delays, neutralizing 3GPP’s attempt to reduce the latency. We address RLC’s related buffer delays and present two solutions: (i) we enhance the 3GPP standard and propose a bufferbloat avoidance algorithm, and (ii) we propose a RB scheduler for circumventing the added sojourn time caused by the packet segmentation/reassembly procedure. Both solutions are implemented and extensively evaluated along with other state-of-the-art proposals in a testbed to verify their suitability and effectiveness under realistic conditions of use (i.e., by considering Modulation and Coding Scheme (MCS) variations, slices, different traffic patterns and off-the-shelf equipment). The results reveal current 3GPP deficits in its QoS model to address the bufferbloat and the contribution of the segmentation/reassembly procedure to the total delay.

Using sensor-rich smartphones to sense various contexts attracts much attention, such as transportation mode recognition. Local solutions make efforts to achieve trade-offs among detection accuracy, delay, and battery usage. We propose a real-time recognition model consisting of two long short-term memory classifiers with different sequence lengths. The shorter one is a binary classifier distinguishing elevator scene and the longer one implements a finer classification among bus, subway, high-speed railway, and others. Light-weighted sensors are employed with a much smaller sampling rate (10Hz) compared with previous works. A two-stage setting makes it robust to scenes with different duration and therefore reduces the latency of recognition greatly. Further, the real-time system refines the classification results and attains smoothed predictions. We present experiments on accuracy and resource usage and prove that our system realizes a latency-low and power-efficient scene recognition approach by trading off a reasonable performance loss (averaged recall of 92.22%).

Time-Sensitive Networking (TSN) is a new set of amendments that guarantee the quality of service (QoS) of time-critical and safety-critical Ethernet applications. The guard band mechanism prevents time-sensitive traffic from colliding with non-time-sensitive traffic, causing potential bandwidth waste. Moreover, most of the existing scheduling strategies only consider Audio Video Bridging (AVB) traffic and Time-Triggered (TT) traffic, resulting in Best Effort (BE) traffic not being scheduled de facto. This article proposes a new system design and scheduling strategy for TSN switches. The size-aware group weighted round robin (SGWRR) strategy is proposed to schedule AVB queues according to subperiods, reducing the average scheduling intervals of the AVB frames. The entire scheduling cycle is divided into a protected slot and an unprotected slot, and dynamic programming is used to minimize guard band waste. An old queue priority (OQP) strategy is also proposed to provide scheduling opportunities for BE queues. A simulation of OMNet++ shows that SGWRR can achieve low average scheduling intervals while improving bandwidth utilization by 5.66% and that OQP can enhance BE scheduling opportunities by 21.9% under our experimental conditions compared with existing methods.

In recent years, in order to provide worldwide broadband Internet access services, many mega-constellation projects have been proposed. Traditional ground-based and space-based telecommand systems only rely on a single path for data transmission, which is vulnerable once the path fails. This paper utilizes inter-satellite-links (ISLs) in the constellation network to reduce the risk of data transmission failure, and proposes the failure-tolerant and low-latency redundant multi-path routing algorithm (RMPR). RMPR transmits multiple data copies on multiple shortest edge-disjoint paths according to the optimal proportions with the minimum delay. Compared with traditional single-path routing and backup multi-path routing, RMPR ensures both reliability and timeliness in telecommand system.

Buffer-aided (BA) relaying improves the diversity of cooperative networks often at the cost of increasing end-to-end packet delays. This characteristic renders BA relaying unsuitable for delay-sensitive applications. However, the increased diversity makes BA relaying appealing for ultra-reliable communications. Towards enabling ultra-reliable low-latency communication (URLLC), we aim at enhancing BA relaying for supporting delay-sensitive applications. In this paper, reliable full-duplex (FD) network operation is targeted and for this purpose, hybrid relay selection algorithms are formulated, combining BA successive relaying (SuR) and delay- and diversity-aware (DDA) half-duplex (HD) algorithms. In this context, a hybrid FD DDA algorithm is presented, namely LoLa4SOR, switching between SuR and HD operation. Additionally, a low-complexity distributed version is given, namely d-LoLa4SOR, providing a trade-off among channel state information requirements and performance. The theoretical analysis shows that the diversity of LoLa4SOR equals to two times the number of available relays $K$ , i.e., $2K$ , when the buffer size $L$ is greater than or equal to 3. Comparisons with other HD, SuR and hybrid algorithms reveal that LoLa4SOR offers superior outage and throughput performance while, the average delay is reduced due to SuR-based FD operation and the consideration of buffer state information for relay-pair selection. d-LoLa4SOR, as one of the few distributed algorithms in the literature, has a reasonable performance that makes it a more practical approach.

The advent of the Internet-of-Things (IoT) and proliferation of wireless devices and systems have put stringent requirements on reliability and latency, in addition to the scarcity of energy and spectrum resources. More importantly, ultra-reliability and low-latency (URLL) combined with concepts of energy-harvesting (EH) and cognitive-radio (CR) make the analysis of IoT networks much more complex. This paper analyzes the performance of uplink EH-CR-IoT networks with URLL requirements. Analytical expressions for IoT network metrics, namely, average packet latency, reliability, and energy-efficiency are derived, while incorporating diversity transmissions under the finite blocklength (FBL) regime. The effect of network parameters, such as number of resource blocks allocated to each IoT user equipment (UE), blocklength, and number of packet replicas is examined on the network metrics, and their tradeoffs are discussed. Finally, the derived expressions are utilized to maximize the energy-efficiency of the IoT UEs subject to energy-causality and URLL constraints.

Internet-of-Things (IoT) networks have recently emerged to provide massive connectivity for many application scenarios and services. Additionally, developing spectrum-access strategies for a large number of nodes with sporadic data traffic behaviors in IoT networks has attracted much attention recently. However, developing such strategies becomes more challenging when ultra-reliable low-latency (URLL) transmissions are required. As IoT networks entail spectrum-efficient transmission schemes, non-orthogonal multiple-access (NOMA) has emerged as a key enabler for such networks. On the other hand, grant-free random-access (RA) techniques are particularly promising for high spectral-efficiency and massive connectivity, since they reduce signaling overhead, and packet latency. Therefore, in this paper, uplink RA-NOMA IoT networks with clustered IoT devices is studied, where short packet and diversity transmissions are adopted to meet the URLL requirements. To reduce the negative effect of diversity transmission on packet latency, multiple replicas of packets are accommodated within different resource blocks (RBs) in the same transmission time interval (TTI). The analytical expressions of network metrics, namely, average packet latency, reliability, and GoodPut are derived. Furthermore, the effect of the number of packet replicas, blocklength, and cluster size on the network metrics is evaluated. Finally, the analytical derivations are utilized to find the optimal values for the number of packet replicas, blocklength, and power control parameters, such that the network GoodPut is maximized, subject to URLL constraints.

Event cameras are bio-inspired sensors that capture intensity changes of pixels individually, and generate asynchronous and independent “events”. Due to the fundamental difference from the conventional cameras, most research on event cameras builds a global event frame by grouping events according to their timestamps or their number to employ traditional computer vision algorithms. However, in order to take advantage of event cameras, it makes sense to generate asynchronous output on an event-by-event basis. In this paper, we propose an optical flow estimation algorithm with low latency and robustness to various scenes to utilize the advantage of the event camera by enhancing the existing optical flow algorithm. Furthermore, we estimate angular velocity with low latency using the proposed optical flow stream. For the validation of algorithms, we evaluate the accuracy and latency of optical flow with publicly available datasets. Moreover, we assess the performance of the proposed angular velocity estimation in comparison to the existing algorithms. Both validations suggest that our asynchronous optical flow shows comparable accuracy to the existing algorithms and the latency is reduced by half compared to the existing block matching algorithm on average. Also, our angular velocity estimation is superior to the existing algorithms in terms of accuracy and robustness while showing low latency within 15 ms consistently.

Time-sensitive networking (TSN) provides end-to-end data transmission with extremely low-latency and high-reliability over ethernet,which is suitable for time-sensitive applications,widely used in automatic driving,industry of internet and other scenarios.Firstly,the characteristics of TSN were summarized,the working principles and features of TSN standards were elaborated in detail,the network technology that provided deterministic and reliable data transmission in wireless network was especially introduced,as wireless TSN technology.In addition,the application cases of TSN were briefly analyzed.The challenges and problems of TSN and wireless TSN technology and their application in industrial scenarios were discussed,and the future research directions were prospected.

Deep learning has attracted a lot of attention from both academic, as well as, industrial parties mainly due to its success when working large datasets and its ability to improve performance by scaling up the size of the models. However, the current trends of training state-of-the-art deep learning models are worrisome. Recent data show that training cutting-edge models is vastly energy inefficient and pose a threat to the democratisation of this technology: the resources required to train a model might be accessible only by a few large corporations in the near future. Moreover, executing trained state-of-the-art deep learning models on mobile devices with limited resources is currently not possible due to the large amounts of computations, memory and energy requirements these models need. Neuromorphic engineering is a relatively recent interdisciplinary research field that attempts to simulate neurons and synapses directly on hardware and at a level that is closer to biology. The advantage of this approach is that because neurons are simulated in an asynchronous manner the overall energy consumption is very low since neurons that do not participate in the computations consume nearly zero energy. While a method to train neural networks directly on neuromorphic devices has yet to be discovered it has already been demonstrated that executing trained neural networks on neuromorphic platforms comes with large energy savings and lower prediction latencies.

The development of intelligent Internet of vehicles (IoV) is based on communication technology, especially the quantum communication of hybrid entangled states based on orbital angular momentum (OAM). The quantum key distribution (QKD) method is demonstrated using hybrid entangled states with multi-degree of freedom and high purity based on OAM. First, the polarization entangled photon pairs are produced by two type I BBO crystals by means of spontaneous parametric down-conversion (SPDC). The polarization-OAM hybrid entangled states are created by q-plate (QP) to realize QKD. It is found that the polarization entangled photon pairs have the characteristics of OAM. A single mode fiber (SMF) is proposed to filter the topological charge non-zero photons and purify the polarization entangled photon pairs. Then the purification setup with M-Z interferometer and beam rotator (BR) is presented which can purify the polarization-OAM hybrid entangled states. The high purity polarization-OAM hybrid entangled states are implemented, and the QP conversion rate of 3 secondary feedbacks is 99.84% theoretically. Analysis indicates that precise purity polarization-OAM hybrid entangled state can increase the fidelity of information and improve the anti-interference ability in this program without mutually unbiased bases (MUBs). The photon utilization rate, energy-efficient and low-latency communication can be greatly improved by using the OAM carrying information.

The scattered Optical Network Units (ONUs) in an optical access network have different propagation delays. In an Ethernet passive optical network (EPON) adopting the traditional Interleaved Polling with Adaptive Cycle Time (IPACT) scheme, such ONU propagation delay difference will waste network resources and will degrade both network delay performance and network energy efficiency in delivering low-latency services. In this article, to deal with the heterogeneous ONU propagation delays problem, two solutions are proposed and investigated. The first solution, namely the Upstream Postponing with ONU Dozing (UP-OD) scheme, is to properly postpone the upstream transmissions of those ONUs having relatively short propagation delays to improve channel utilization efficiency, and ONU doze mode is incorporated to enhance network energy efficiency. The second solution, namely the Identical Fiber Length with ONU Sleeping (IFL-OS) scheme, is to adopt an identical distribution fiber length for ONUs to enhance channel utilization, and ONU sleep mode is incorporated for energy consumption reduction. Simulation results show that both the UP-OD scheme and the IFL-OS scheme reduce network delay and improve network energy efficiency in delivering low-latency (

Non-orthogonal multiple-access (NOMA) has recently been proposed to improve throughput and spectrum-efficiency of 5G cellular networks and beyond. It is also a key enabler for ultra-reliable and low-latency (URLL) communications. Moreover, the Internet-of-Things (IoT) paradigm has emerged to practically provide massive connectivity for smart devices and systems, which entails spectrum- and energy-efficient transmission schemes. To this aim, NOMA and energy-harvesting (EH) solutions have been put forth to address such demands, making the combination of such technologies inevitable in NOMA-based URLL-EH-IoT networks. On the other hand, random-access (RA) techniques are the key solution to enable massive URLL-EH-IoT networks, since they reduce signaling overhead, packet latency, and energy consumption when massive numbers of clustered IoT devices with sporadic traffic behavior are considered. In this paper, uplink RA-NOMA in URLL-EH-IoT networks with short packet and diversity transmissions is studied and analyzed. Network metrics-such as average packet latency, reliability, and GoodPut-are derived for the RA-NOMA scenario and compared with its RA-OMA counterpart to explore the advantages of RA-NOMA over RA-OMA. Moreover, the analytical derivations have been validated and shown to coincide with the simulation results. Furthermore, the effect of the transmission diversity and number of data bits per blocklength on the different network metrics are extensively evaluated. Lastly, the analytical derivations are utilized to find the optimum values of the IoT nodes' transmit power, number of packet replicas, and number of transmitted data bits per blocklength, such that the maximum sum-GoodPut of a RA-NOMA IoT cluster is achieved, subject to URLL constraints.

Critical systems such as drone control or power grid control applications rely on embedded devices capable of a real-time response. While much research and advancements have been made to implement low-latency and real-time characteristics, the security aspect has been left aside. All current real-time operating systems available for industrial embedded devices are implemented in the C programming language, which makes them prone to memory safety issues. As a response to this, Tock, an innovative secure operating system for embedded devices written completely in Rust, has recently appeared. The only downside of Tock is that it lacks the low-latency real-time component. Therefore, the purpose of this research is to leverage the extended Berkeley Packet Filter technology used for efficient network traffic processing and to add the low-latency capability to Tock. The result is a secure low-latency operating system for embedded devices and microcontrollers capable of handling interrupts at latencies as low as 60 µs.

Video transmission bandwidth can be substantially increased by concurrent transmission through multiple radio interfaces introduced by heterogeneous wireless networks. However, delivering high-quality real-time videos with stringent end-to-end delay constraints is still challenging due to the time-varying multipath channel status. Thus, to integrate available multipath bandwidth and guarantee low end-to-end delay, this paper investigates a real-time concurrent multipath video transmission scheme in heterogeneous access networks. First, we present a multipath buffer analysis model (MBAM) to derive the lower and upper bounds of the target video frame bits. Second, given the low-latency and received video quality smoothness, we propose a buffer-driven rate control and packet distribution (BRCPD) algorithm aided by frame-level rate control and multipath transmission buffer awareness based on MBAM. Finally, we implement the proposed application-layer solution BRCPD algorithm in a real-world testbed. The experiment results verify that different from existing multipath video transmission schemes, the proposed algorithm is able to leverage the MBAM-based frame-level rate control to guarantee the target low end-to-end delay. In particular, the BRCPD algorithm is able to guarantee an overdue loss rate of less than 5% under strictly limited delay constraints (250 ms) in the real-world testbed.

With the advent of low-cost, embedded sensor-actuator devices, the applications of cyber-physical systems have spread multi-fold in domains like infrastructure, manufacturing, automation, etc. Wireless sensor-actuator networks (WSANs) act as the backbone for applications in these domains. Typical WSAN deployments focus on energy-efficiency (in-turn lifetime) as replacing batteries is labor intensive and expensive. However, many CPS applications require highly-reliable data delivery with strict time bounds. Unfortunately, the classical approach of scheduling/prioritizing flows for bounded time communication is hard to implement with energy-constrained embedded devices. In this work, we present FLEET, a communication primitive that guarantees timely data delivery with 1) low latency by scheduling a maximum number of end-to-end flows within a short time span; 2) highly energy-efficient networking; and 3) reliable data delivery. Using a smart parallelization technique, FLEET achieves simultaneous transmissions while guaranteeing data delivery. This reduces the average duty-cycle of the nodes and makes it more energy-efficient than many state-of-the-art protocols. By combining multiple routing strategies, FLEET not only simplifies the schedulability problem but also accommodates more flows within a time span reducing delay considerably. Overall, with respect to the state of the art, FLEET offers a delay and duty cycling reduction by 2.2 and 2.8 times, respectively.

The authenticated key exchange (AKE) protocol can ensure secure communication between a client and a server in the electricity transaction of the Energy Internet of things (EIoT). Park proposed a two-factor authentication protocol 2PAKEP, whose computational burden of authentication is evenly shared by both sides. However, the computing capability of the client device is weaker than that of the server. Therefore, based on 2PAKEP, we propose an authentication protocol that transfers computational tasks from the client to the server. The client has fewer computing tasks in this protocol than the server, and the overall latency will be greatly reduced. Furthermore, the security of the proposed protocol is analyzed by using the ROR model and GNY logic. We verify the low-latency advantage of the proposed protocol through various comparative experiments and use it for EIoT electricity transaction systems in a Metaverse scenario.

In healthcare, there are rapid emergency response systems that necessitate real-time actions where speed and efficiency are critical; this may suffer as a result of cloud latency because of the delay caused by the cloud. Therefore, fog computing is utilized in real-time healthcare applications. There are still limitations in response time, latency, and energy consumption. Thus, a proper fog computing architecture and good task scheduling algorithms should be developed to minimize these limitations. In this study, an Energy-Efficient Internet of Medical Things to Fog Interoperability of Task Scheduling (EEIoMT) framework is proposed. This framework schedules tasks in an efficient way by ensuring that critical tasks are executed in the shortest possible time within their deadline while balancing energy consumption when processing other tasks. In our architecture, Electrocardiogram (ECG) sensors are used to monitor heart health at home in a smart city. ECG sensors send the sensed data continuously to the ESP32 microcontroller through Bluetooth (BLE) for analysis. ESP32 is also linked to the fog scheduler via Wi-Fi to send the results data of the analysis (tasks). The appropriate fog node is carefully selected to execute the task by giving each node a special weight, which is formulated on the basis of the expected amount of energy consumed and latency in executing this task and choosing the node with the lowest weight. Simulations were performed in iFogSim2. The simulation outcomes show that the suggested framework has a superior performance in reducing the usage of energy, latency, and network utilization when weighed against CHTM, LBS, and FNPA models.

Abstract In this paper, the existing ad hoc on demand multipath distance vector (AOMDV) routing scheme for vehicular ad hoc networks (VANETs) is extended to a reliable low-latency multipath routing (RLLMR) scheme based on multipath link reliability, capable of determining the reliable routes preemptively. Here, the link reliability refers to the probability that a direct transmission link among any two vehicles remains constantly available for a specific period of time, which can be computed based on the position, route, and velocity of the vehicles to facilitate the reliable routing process in VANETs. In the proposed RLLMR scheme, the mathematical distribution of vehicles movements and link breakages is also considered to increase the reliability of the vehicular networks. The simulation results show that proposed RLLMR scheme performs better compared to existing schemes in terms of latency, reliability, throughput, and energy consumption at the cost of marginally increased routing overhead.

Spiking neural networks (SNNs) have attracted many researchers’ interests due to its biological plausibility and event-driven characteristic. In particular, recently, many studies on high-performance SNNs comparable to the conventional analog-valued neural networks (ANNs) have been reported by converting weights trained from ANNs into SNNs. However, unlike ANNs, SNNs have an inherent latency that is required to reach the best performance because of differences in operations of neuron. In SNNs, not only spatial integration but also temporal integration exists, and the information is encoded by spike trains rather than values in ANNs. Therefore, it takes time to achieve a steady-state of the performance in SNNs. The latency is worse in deep networks and required to be reduced for the practical applications. In this work, we propose a pre-charged membrane potential (PCMP) for the latency reduction in SNN. A variety of neural network applications (e.g., classification, autoencoder using MNIST and CIFAR-10 datasets) are trained and converted to SNNs to demonstrate the effect of the proposed approach. The latency of SNNs is successfully reduced without accuracy loss. In addition, we propose a delayed evaluation method (DE), by which the errors during the initial transient are discarded. The error spikes occurring in the initial transient is removed by DE, resulting in the further latency reduction. DE can be used in combination with PCMP for further latency reduction. Finally, we also show the advantages of the proposed methods in improving the number of spikes required to reach a steady-state of the performance in SNNs for energy-efficient computing.

The ability to control a behavioral task or stimulate neural activity based on animal behavior in real-time is an important tool for experimental neuroscientists. Ideally, such tools are noninvasive, low-latency, and provide interfaces to trigger external hardware based on posture. Recent advances in pose estimation with deep learning allows researchers to train deep neural networks to accurately quantify a wide variety of animal behaviors. Here, we provide a new DeepLabCut-Live! package that achieves low-latency real-time pose estimation (within 15 ms, >100 FPS), with an additional forward-prediction module that achieves zero-latency feedback, and a dynamic-cropping mode that allows for higher inference speeds. We also provide three options for using this tool with ease: (1) a stand-alone GUI (called DLC-Live! GUI), and integration into (2) Bonsai, and (3) AutoPilot. Lastly, we benchmarked performance on a wide range of systems so that experimentalists can easily decide what hardware is required for their needs.

With the emergence of the fifth generation (5G) wireless networks, not only is the increase in mobile broadband targeted, but also the support of various novel use cases, such as industrial automation, autonomous vehicles, e-health, and Internet of Things together with their requirements leading to highly heterogeneous wireless networks. This requires a re-design of the network architecture to ensure the coexistence of these use cases and guarantee user experience and service requirements. Therefore, 5G networks will be highly flexible and support online learning and autonomous decision making capabilities in a centralized and distributed manner to ensure highly efficient management of wireless and network resources. In this paper, the main features enabling flexibility and autonomy in 5G networks are discussed together with potential applications in different layers of the wireless network.

Neurofeedback (NFB) is a real-time paradigm, where subjects learn to volitionally modulate their own brain activity recorded with electroencephalographic (EEG), magnetoencephalographic (MEG) or other functional brain imaging techniques and presented to them via one of sensory modalities: visual, auditory or tactile. NFB has been proposed as an approach to treat neurological conditions and augment brain functions. Although the early NFB studies date back nearly six decades ago, there is still much debate regarding the efficiency of this approach and the ways it should be implemented. Partly, the existing controversy is due to suboptimal conditions under which the NFB training is undertaken. Therefore, new experimental tools attempting to provide optimal or close to optimal training conditions are needed to further exploration of NFB paradigms and comparison of their effects across subjects and training days. To this end, we have developed open-source NFBLab, a versatile, Python-based software for conducting NFB experiments with completely reproducible paradigms and low-latency feedback presentation. Complex experimental protocols can be configured using the GUI and saved in NFBLab's internal XML-based language that describes signal processing tracts, experimental blocks and sequences including randomization of experimental blocks. NFBLab implements interactive modules that enable individualized EEG/MEG signal processing tracts specification using spatial and temporal filters for feature selection and artifacts removal. NFBLab supports direct interfacing to MNE-Python software to facilitate source-space NFB based on individual head models and properly tailored individual inverse solvers. In addition to the standard algorithms for extraction of brain rhythms dynamics from EEG and MEG data, NFBLab implements several novel in-house signal processing algorithms that afford significant reduction in latency of feedback presentation and may potentially improve training effects. The software also supports several standard BCI paradigms. To interface with external data acquisition devices NFBLab employs Lab Streaming Layer protocol supported by the majority of EEG vendors. MEG devices are interfaced through the Fieldtrip buffer.

Stochastic computing has been recently proposed for the hardware implementation of both low-density parity-check (LDPC) decoders and turbo decoders, which facilitate near-optimal error correction capabilities in wireless communication applications. Previous contributions have demonstrated that stochastic LDPC decoders offer an attractive tradeoff between their error correction capabilities, hardware performance, and timing-error tolerance. Motivated by this, we propose a pair of stochastic turbo decoder (STD) designs having significantly enhanced timing-error tolerance and significantly reduced processing latency. Moreover, we characterize the tradeoffs between chip area, energy efficiency, latency, throughput, and error correction capabilities of both the timing-error-tolerant STD and of the reduced-latency STD. We demonstrate that our proposed timing-error-tolerant STD operated at 1.20 V, with a clock period of 2.2 ns and in the presence of a three-standard deviation power supply variation of 7%, exhibits an unimpaired performance, compared with the state-of-the-art STD, operated at 1.20 V and 4 ns and with no power supply variations. This corresponds processing throughput improvement by a factor of 2.42 and energy consumption reduction by a factor of 4. Finally, we demonstrate that our proposed reduced-latency STD has a processing latency that is an order of magnitude lower than that of the state-of-the-art STD. This is despite reducing the chip area by a factor of 4, increasing the processing throughput by a factor of 65, while consuming only 0.005 times the energy of the state-of-the-art STD, when using binary phase-shift keying for communication over an additive white Gaussian noise channel having Eb/N0 = 3 dB.

To fulfill the increasing demand on low-latency content distribution, this paper considers content distribution using generation-based network coding with the belief propagation decoder. We propose a framework to design generation-based network codes via characterizing them as building an irregular graph, and design the code by evaluating the graph. The and-or tree evaluation technique is extended to analyze the decoding performance. By allowing for non-constant generation sizes, we formulate optimization problems based on the analysis to design degree distributions from which generation sizes are drawn. Extensive simulation results show that the design may achieve both low decoding cost and transmission overhead as compared to existing schemes using constant generation sizes, and satisfactory decoding speed can be achieved. The scheme would be of interest to scenarios where (1) the network topology is not known, dynamically changing, and/or has cycles due to cooperation between end users, and (2) computational/memory costs of nodes are of concern but network transmission rate is spare.

A research contribution focusing on the Quantum Key Distribution (QKD)-enabled solutions assisting in the security framework of an optical 5G fronthaul segment is presented. We thoroughly investigate the integration of a BB84-QKD link, operating at telecom band, delivering quantum keys for the Advanced Encryption Standard (AES)-256 encryption engines of a packetized fronthaul layer interconnecting multiple 5G terminal nodes. Secure Key Rate calculations are studied for both dedicated and shared fiber configurations to identify the attack surface of AES-encrypted data links in each deployment scenario. We also propose a converged fiber-wireless scenario, exploiting a mesh networking extension operated by mmWave wireless links. In addition to the quantum layer performance, emphasis is placed on the strict requirements of 5G-oriented optical edge segments, such as the latency and the availability of quantum keys. We find that for the dark fiber case, secret keys can be distilled at fiber lengths much longer than the maximum fiber fronthaul distance corresponding to the round-trip latency barrier, for both P2P and P2MP topologies. On the contrary, the inelastic Raman scattering makes the simultaneous transmission of quantum and classical signals much more challenging. To counteract the contamination of noise photons, a resilient classical/QKD coexistence scheme is adopted. Motivated by the recent advancements in quantum technology roadmap, our analysis aims to introduce the QKD blocks as a pillar of the quantum-safe security framework of the 5G/B5G-oriented fronthaul infrastructure.

This paper aims to design an online, low-latency, and high-performance speech recognition system using a bidirectional long short-term memory (BLSTM) acoustic model. To achieve this, we adopt a server-client model and a context-sensitive-chunk-based approach. The speech recognition server manages a main thread and a decoder thread for each client and one worker thread. The main thread communicates with the connected client, extracts speech features, and buffers the features. The decoder thread performs speech recognition, including the proposed multichannel parallel acoustic score computation of a BLSTM acoustic model, the proposed deep neural network-based voice activity detector, and Viterbi decoding. The proposed acoustic score computation method estimates the acoustic scores of a context-sensitive-chunk BLSTM acoustic model for the batched speech features from concurrent clients, using the worker thread. The proposed deep neural network-based voice activity detector detects short pauses in the utterance to reduce response latency, while the user utters long sentences. From the experiments of Korean speech recognition, the number of concurrent clients is increased from 22 to 44 using the proposed acoustic score computation. When combined with the frame skipping method, the number is further increased up to 59 clients with a small accuracy degradation. Moreover, the average user-perceived latency is reduced from 11.71 s to 3.09–5.41 s by using the proposed deep neural network-based voice activity detector.

We present the first hardware implementations of Diffie-Hellman key exchange based on the Kummer surface of Gaudry and Schost’s genus-2 curve targeting a 128-bit security level. We describe a single-core architecture for lowlatency applications and a multi-core architecture for high-throughput applications. Synthesized on a Xilinx Zynq-7020 FPGA, our architectures perform a key exchange with lower latency and higher throughput than any other reported implementation using prime-field elliptic curves at the same security level. Our single-core architecture performs a scalar multiplication with a latency of 82 microseconds while our multicore architecture achieves a throughput of 91,226 scalar multiplications per second. When compared to similar implementations of Microsoft’s Fourℚ on the same FPGA, this translates to an improvement of 48% in latency and 40% in throughput for the single-core and multi-core architecture, respectively. Both our designs exhibit constant-time execution to thwart timing attacks, use the Montgomery ladder for improved resistance against SPA, and support a countermeasure against fault attacks.

Parallel hardware designed for image processing promotes vision-guided intelligent applications. With the advantages of high-throughput and low-latency, streaming architecture on FPGA is especially attractive to real-time image processing. Notably, many real-world applications, such as region of interest (ROI) detection, demand the ability to process images continuously at different sizes and resolutions in hardware without interruptions. FPGA is especially suitable for implementation of such flexible streaming architecture, but most existing solutions require run-time reconfiguration, and hence cannot achieve seamless image size-switching. In this paper, we propose a dynamically-programmable buffer architecture (D-SWIM) based on the Stream-Windowing Interleaved Memory (SWIM) architecture to realize image processing on FPGA for image streams at arbitrary sizes defined at run time. D-SWIM redefines the way that on-chip memory is organized and controlled, and the hardware adapts to arbitrary image size with sub-100 ns delay that ensures minimum interruptions to the image processing at a high frame rate. Compared to the prior SWIM buffer for high-throughput scenarios, D-SWIM achieved dynamic programmability with only a slight overhead on logic resource usage, but saved up to 56 % of the BRAM resource. The D-SWIM buffer achieves a max operating frequency of 329.5 MHz and reduction in power consumption by 45.7 % comparing with the SWIM scheme. Real-world image processing applications, such as 2D-Convolution and the Harris Corner Detector, have also been used to evaluate D-SWIM’s performance, where a pixel throughput of 4.5 Giga Pixel/s and 4.2 Giga Pixel/s were achieved respectively in each case. Compared to the implementation with prior streaming frameworks, the D-SWIM-based design not only realizes seamless image size-switching, but also improves hardware efficiency up to 30 × .