Search

Nowadays multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to reduced harmonic distortions, lower electromagnetic interference, and higher DC link voltages. However, the increased number of components, complex PWM control, voltage-balancing problem, and component failure in the circuit are some of the disadvantages. The topology suggested in this paper provides a DC voltage in the shape of a staircase that approximates the rectified shape of a commanded sinusoidal wave to the bridge inverter, which in turn alternates the polarity to produce an AC voltage with low total harmonic distortion and power loss. This topology requires fewer components and hence it leads to the reduction of overall cost and complexity particularly for higher output voltage levels. The component fault diagnostic algorithm is developed using wavelets transform tool. Finally an experimental prototype is developed and validated with the simulation results. Keywords: Field programmable gate array (FPGA), In-phase disposition (IPD) PWM, Least number of switching devices, Multi level inverter, Total harmonic distortion, Wavelet transform tool