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In this work, single photon avalanche diodes (SPADs) were fabricated using the standard 180 nm complementary metal-oxide semiconductor process. Their small size of 15–16 μ m and low operating voltage made it possible to easily integrate them with readout circuits for compact on-chip sensors, particularly those used in the radiation sensor network of a nuclear plant. Four architectures were proposed for the SPADs, with a shallow trench isolation (STI) guard ring and different depletion regions designed to demonstrate the main performance parameters in each experimental configuration. The wide absorption region structure with PSD and a deep N-well could achieve a uniform electric field, resulting in a stable dark count rate (DCR). Additionally, the STI guard ring was implanted to mitigate the premature edge breakdown. A breakdown voltage was achieved for a low operating voltage of 10.75 V. The DCR results showed 286.3 Hz per μm2 at an excess voltage of 0.04 V. A photon detection probability of 21.48% was obtained at 405 nm.

A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated. Foremost, the correctness of the dual modulation effect in GAA-TFETs is demonstrated. Building on that, the model comprehensively considers the effects of the channel depletion region, drain depletion region, and channel inversion charges. Furthermore, a compact current model for GAA-TFETs, based on the derived surface potential expression, is presented, with a discussion on ambipolar conduction—an essential factor for device model integrity. The model’s accuracy and flexibility are validated through TCAD simulations and measurement data from NW-GAA-TFETs, yielding promising results.

Abstract:For the first time, in this research, we introduce ajunctionless tunneling FET (J-TFET) on a uniform p+starting junctionless FET to realize appreciable immunityagainst inherent high ambipolar current (Iamb). So, weutilize two isolated gates with appropriate workfunctionsover the channel and drain regions to create P+IP+N+charge distribution. This structure utilizes a spacebetween the gate-drain electrodes (SGD), to provide aP+IP+N+ structure thanks to the effective electronsdepletion on the drain side. Increasing the SGD, furthereffectively pulls up the bands near the interface betweenthe channel-drain regions, widens the tunneling width fortunneling to occur, and thus in turn reduces the Iamb from5.37×10-7 A/µm to 1.14×10-14 A/µm. Thus, we point outthat the proposed J-TFET can obtain on-current thatsatisfies the expectation of logic applications with highperformance and Ioff that meets the specifications of lowpower characteristics, a phenomenon that is rarelyaccessible with conventional TFETs.

Abstract Owing to the large built‐in field for efficient charge separation, heterostructures facilitate the simultaneous realization of a low dark current and high photocurrent. The lack of an efficient approach to engineer the depletion region formed across the interfaces of heterojunctions owing to doping differences hinders the realization of high‐performance van der Waals (vdW) photodetectors. This study proposes a ferroelectric‐controlling van der Waals photodetector with vertically stacked two‐dimensional (2D) black phosphorus (BP)/indium selenide (In2Se3) to realize high‐sensitivity photodetection. The depletion region can be reconstructed by tuning the polarization states generated from the ferroelectric In2Se3 layers. Further, the energy bands at the heterojunction interfaces can be aligned and flexibly engineered using ferroelectric field control. Fast response, self‐driven photodetection, and three‐orders‐of‐magnitude detection improvements are achieved in the switchable visible or near‐infrared operation bands. The results of the study are expected to aid in improving the photodetection performance of vdW optoelectronic devices.