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Abstract This paper presents simulation and measurement results of a 2–4 GHz octave bandwidth interference suppression circuit. The circuit accomplishes the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The delay is adjusted by varying the drain voltage of cold‐FET connected high electron mobility transistors acting as varactors. Two types of periodically‐loaded delay lines are compared: a uniform and a tapered design. A simple theoretical study, relating the delays and amplitudes in the interferometer circuit branches, is developed to inform the design. Two interference suppression hybrid circuits are implemented, and measurements demonstrate a 25–40 dB notch across the 2.24–4 GHz range for the uniform delay line, and 2.32–4.13 GHz for the tapered design. The return loss for both designs remains below 10 dB. Measurements with two tones spaced 0.5 and 1 GHz for varying tone power are performed to quantify suppression. The circuit can handle an input power of 37 dBm and maintains performance with two simultaneous 25 dBm tones spaced 0.5 GHz apart. Linearity is characterised with 10 MHz two‐tone measurements, and the circuit demonstrates a 3rd‐order intercept input power larger than 30 dBm for control biases above −12 V.

Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications, such as lidar, radar, and artificial intelligence. Silicon photonics has unique advantages of ultra-high integration density as well as CMOS compatibility, and thus makes it possible to develop large-scale programmable optical signal processors. The challenge is the high silicon waveguides propagation losses and the high calibration complexity for all tuning elements due to the random phase errors. In this paper, we propose and demonstrate a programmable silicon photonic processor for the first time by introducing low-loss multimode photonic waveguide spirals and low-random-phase-error Mach-Zehnder switches. The present chip-scale programmable silicon photonic processor comprises a 1×4 variable power splitter based on cascaded Mach-Zehnder couplers (MZCs), four Ge/Si photodetectors, four channels of thermally-tunable optical delaylines. Each channel consists of a continuously-tuning phase shifter based on a waveguide spiral with a micro-heater and a digitally-tuning delayline realized with cascaded waveguide-spiral delaylines and MZSs for 5.68 ps time-delay step. Particularly, these waveguide spirals used here are designed to be as wide as 2 µm, enabling an ultralow propagation loss of 0.28 dB/cm. Meanwhile, these MZCs and MZSs are designed with 2-µm-wide arm waveguides, and thus the random phase errors in the MZC/MZS arms are negligible, in which case the calibration for these MZSs/MZCs becomes easy and furthermore the power consumption for compensating the phase errors can be reduced greatly. Finally, this programmable silicon photonic processor is demonstrated successfully to verify a number of distinctively different functionalities, including tunable time-delay, microwave photonic beamforming, arbitrary optical signal filtering, and arbitrary waveform generation.

Abstract This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond that set by the chosen technology is investigated. A cascode tri‐state inverter is proposed to improve the isolation between the input and output of interpolation cells so as to improve the linearity of the time interpolator. Design considerations that critically affect the linearity of the DTC are examined in detail. The impact of the slope of the inputs of the time interpolator on the latency and linearity of the interpolator is analysed and the maximum slope of the input of interpolators yielding the minimum latency without sacrificing linearity, is obtained. The timing errors of DTC are investigated and the considerations of the layout of the DTC are examined. The DTC is designed in a TSMC 65 nm 1.0 V CMOS technology and analysed using Spectre with BSIM3V3 device models. Post‐layout simulation results show the DTC offers 3.6 ps resolution, 580 MS/s conversion rate, and consumes 383 μW.

The adoption of non-linear magnetic devices in Radio Frequency (RF) systems has been relatively slow due to their unique characteristics that do not lend themselves well to traditional design tools and methodologies. Herein we present the practical considerations in employing such devices in modern RF system design with an emphasis on realizable improvements in performance and adaptability in addition to the common design methodology that has been adopted to account for their unique behavior. Specifically, this article begins by presenting how a standalone nonlinear device such as a Frequency Selective Limiter (FSL) can enable a higher-level subsystem such as the Frequency Selective Canceller (FSC). This discussion sheds light on the importance of characterizing the behavior of an FSL and how this behavior is different from other, more traditional RF components such as a Pin Diode Limiter, as explained in the second part of the article. Lastly, a Magnetostatic Wave (MSW) delay line that leverages the recent advancements in non-linear magnetic device design is introduced in order to provide an attractive alternative to traditional delay lines. A more complete understanding of system-level performance benefits and device-level functionality will undoubtedly facilitate the widescale deployment of nonlinear magnetic devices to help mitigate spectrum congestion challenges faced by modern and future RF systems.

Constructions of meander slow-wave systems with additional shields grounded at different positions are presented. The construction of meander slow-wave systems with additional shields grounded at both edges is investigated in detail. The influence of the main constructive parameters on the electrical characteristics of meander slow-wave systems with additional shields grounded at both edges is evaluated. The main constructive parameters of the investigated system are: the length of the conductor, the width of meander conductor, the width of additional shield, and the width of the gap between adjacent meander conductors.

It has since long been known that surface acoustic wave (SAW) devices, resonators as well as delay lines, can be used as passive wireless sensors for physical quantities, like temperature and pressure, as well as gas sensors or identification-tags (ID-tags). The sensors are robust, work passively without a battery, can be applied at high temperatures, and provide a high resolution. Nevertheless, if the devices are used wirelessly in an industrial environment, several constraints have to be taken into account, especially when more than one quantity or device needs to be measured at the same time. The paper addresses the challenges that must be tackled when establishing multi-sensor-wireless-readout for industrial applications. Major issues here are the legal regulations for industrial, scientific and medical frequency bands (ISM-bands), as well as sampling time and costs, which impose severe restrictions to any system design. We describe several design approaches and their constraints. We successfully designed sensors based on reflective delay lines that allow the parallel readout of four independent temperature sensors in the 2.45 GHz ISM-band. These devices were fabricated and positively tested, demonstrating the applicability of SAW sensors for industrial applications.

In this paper, we report a direct comparison between coupled resonator optical waveguides (CROWs) and photonic crystal waveguides (PhCWs), which have both been exploited as tunable delay lines. The two structures were fabricated on the same silicon-on-insulator (SOI) technological platform, with the same fabrication facilities and evaluated under the same signal bit-rate conditions. We compare the frequency- and time-domain response of the two structures; the physical mechanism underlying the tuning of the delay; the main limits induced by loss, dispersion, and structural disorder; and the impact of CROW and PhCW tunable delay lines on the transmission of data stream intensity and phase modulated up to 100 Gb/s. The main result of this study is that, in the considered domain of applications, CROWs and PhCWs behave much more similarly than one would expect. At data rates around 100 Gb/s, CROWs and PhCWs can be placed in competition. Lower data rates, where longer absolute delays are required and propagation loss becomes a critical issue, are the preferred domain of CROWs fabricated with large ring resonators, while at data rates in the terabit range, PhCWs remain the leading technology.

This study provides an in-depth review of the principles, architectures and design techniques of CMOS time-to-digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs. Sampling TDCs including direct-counter TDCs, tapped delay-line TDCs, pulse-shrinking delay-line TDCs, cyclic pulse-shrinking TDCs, direct-counter TDCs with interpolation, vernier TDCs, flash TDCs, successive approximation TDCs and pipelined TDCs are studied and their pros and cons are compared. Noise-shaping TDCs that reduce in-band noise below technology limit are investigated. These TDCs include gated ring oscillator TDCs, switched ring oscillator TDCs, relaxation oscillator TDCs, ΔΣ TDCs and MASH TDCs. The performance of sampling and noise-shaping TDCs is compared. The direction of future research on TDCs is explored.

In this paper, we present a study of integrated optical delay lines (DLs) for application in optical time-division multiplexers. The investigated DLs are formed by spirally folded waveguides. The components were designed in a generic approach and fabricated in multi-project wafer runs on an InP-based platform. The design process and rules, together with characterization results of test structures, are discussed. Static and dynamic measurements were performed for verification of the DLs' performance in the wavelength and time domain. Additionally, a comparison between the simulation and characterization results is given, which confirms good agreement between measured and designed values.