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This paper presents a 6-bit hybrid True Time Delay (TTD) circuit designed for X-band phased array antenna systems. The circuit integrates a conventional transmission-line (T-line) based TTD structure for short delays (1.56 ps, 3.125 ps, 6.25 ps, 12.5 ps) with a Gm-C-based all-pass filter (APF) employing a thermostat method for longer delays (25 ps, 50 ps, 75 ps). Fabricated using the 28nm FD-SOI CMOS process, the proposed TTD achieves delay times up to 100 ps with a fine control step of 1.56 ps. Measurement results validate the circuit’s performance, demonstrating excellent group delay accuracy with an RMS error of less than 1.56 ps across the operating frequency range. Furthermore, all delay states maintain isolation greater than 10 dB and ensure gain variation within ±9 dB at 9 GHz. The proposed TTD circuit provides a low-power, compact solution, which makes it a promising candidate for wideband applications requiring agile beam steering while effectively mitigating the beam squint phenomenon. The implemented TTD chip occupies a compact area of 0.54 mm2 and exhibits a power consumption of up to 13.53 mW.

The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.