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Traditionally, neuropsychological testing has assessed processing speed and precision, closely related to the ability to perform high-order cognitive tasks. An individual making a decision under time pressure must constantly rebalance its speed to action in order to account for possible errors. A deficit in processing speed appears to be afrequent disorder caused by cerebral damage — but it can be hard to pinpoint the exact cause of the slowdown. It is therefore important to separate the perceptual-motor component of processing speed from the decision-time component. We present a technique to isolate Reaction Times (RTs): a short digital test to assess the decision-making abilities of individuals by gauging their ability to balance between speed and precision. Our hypothesis is that some subjects willaccelerate, and others slow down in the face of the difficulty. This pilot study, conducted on 83 neurotypical adult volunteers, used images stimuli. The test was designed to measure RTs and correctness. After learning release gesture, the subjects were presented with three tasks: a simple Reaction Time task, a Go/No-Go, and a complex Go/No-Go with 2 simultaneous Choices. All three tasks have in common a perceptual component and a motor response. By measuring the 3 reference points requiring attentional and executive processing, while progressively increasing the conceptual complexity of the task, we were able to compare the processing times for different tasks — thus calculating the deceleration specific to the reaction time linked to difficulty. We defined the difficulty coefficient of a task as being the ratio of the group average time of this task minus the base time/average time of the unit task minus the base time. We found that RTs can be broken down into three elementary, uncorrelated components: Reaction Time, Executive Speed, and Reaction to Difficulty (RD). We hypothesized that RD reflects how the subject reacts to difficulty by accelerating (RD < 0) or decelerating (RD > 0). Thus we provide here a first proof of concept: the ability to measure four axes of the speed-precision trade-off inherent in a subject's fundamental decision making: perceptual-motor speed, executive speed, subject accuracy, and reaction to difficulty. [ABSTRACT FROM AUTHOR]

For reducing the test application time and required tester pins per device, we propose the use of multi-valued logic (MVL) signals, which increases data rate between the device under test (DUT) and automatic test equipment (ATE). An MVL signal sends multiple bits of information per clock cycle on a physical channel. Conversion of signals between binary and MVL is accomplished by digital to analog and analog to digital converters available in the mixed-signal technology. To support MVL test application and avoid reliability issues, we add necessary modifications on ATE and DUT sides. Theoretical calculation and a prototype experiment demonstrate significant data rate increase. We integrate the proposed MVL technique into test methodologies involving reduced pin-count test (RPCT) for multi-core system-on-chip (SoC) and test compression. An actual automatic test equipment (ATE) based test of a DUT shows notable reduction in test application time with MVL test application. [ABSTRACT FROM AUTHOR]

The total logic activity produced in a digital circuit during testing, and hence the total energy consumed, is an invariant of a set of tests. Faster we consume this energy, shorter will the test time be. Thus, to minimize the test time we may maximize the power during test by using a dynamically selectable clock frequency. This idea is exploited in our solution for the problem of finding clock frequencies under the constraints of maximum allowable power and critical path delay. A very efficient but approximate kth-root solution finds k test clock frequencies, which are further optimized by a locally exhaustive search (LES) algorithm. Both solutions have an O( N× k) complexity for finding k clock frequencies when the test runs through N clock cycles, though kth-root solution is about two orders of magnitude faster to compute than LES. In practice, LES gives optimally minimum test time and is matched by the kth-root solution for k ≥ 10. [ABSTRACT FROM AUTHOR]

In this paper we present a web-based distributed fault simulation framework built with standard Java Applet/Servlet technology and the popular platform independent open source database MySQL. Fault simulation plays an important role in digital electronics design flow by creating and evaluating test patterns, identifying and locating the causes of the circuit failures. Because of the rapid increase of the circuit sizes, there is ever growing need for memory and computational power. Our solution allows to seamlessly aggregate many remote computers for one application. We propose a novel collaboration centric computing approach using a participant credit based priority concept. Issues of task partitioning, task allocation, load balancing and model security are also handled. Our primary goal during circuit partitioning has been the decrease of the needed simulation memory to allow working with larger circuits for which conventional simulation methods are not always usable. Our novel method of partitioning produces model slices with no interdependences, suitable for Internet based use. Larger scalability is achieved by using model partitioning along the test pattern set partitioning. [ABSTRACT FROM AUTHOR]

This paper describes a hybrid BIST methodology for testing systems-on-chip. In our hybrid BIST approach a test set is assembled, for each core, from pseudo random test patterns that are generated on-line, and deterministic test patterns that are generated off-line and stored in the system. The deterministic test set is specially designed to shorten the pseudo random test cycle and to target random resistant faults. To support such a test strategy, we have developed several hybrid BIST architectures that target different test scenarios. As the test lengths of the two test sequences is one of the important parameters in the final test cost, we have to find the most efficient combination of those two test sets without sacrificing the test quality. We describe methods for finding the optimal combination of pseudo random and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed up the calculation process. Experimental results have shown the efficiency of the algorithms to find a near-optimal solutions. [ABSTRACT FROM AUTHOR]