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The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this paper. First, analytical equations are derived to provide insight to the FE effect for FinFET devices, and these analytical results are validated by 3-D TCAD simulation and experimental verification. Next, complicated programming and erasing characteristics and transconductance and subthreshold slope (gm/SS) behaviors are completely explained by the nonuniform injection behavior along various corner edges in FinFET. FE allows high program and erase speed and larger memory window. On the other hand, the edge effect complicates the device DC I-V, as well as programming and erasing characteristics, and these must be taken into account in memory circuit design. [ABSTRACT FROM AUTHOR]

This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 μm². This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 Å, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node. [ABSTRACT FROM AUTHOR]

A novel integrated ambient light sensor using nanocrystalline silicon fabricated using low-temperature polysilicon technology has been developed on a display panel. The photosensing structure of the silicon nanocrystals embedded in a dielectric film sandwiched between the bottom metal and top indium-thin-oxide electrodes perfectly eliminates backlight noise, which is a problem typical of conventional p-i-n photodiodes integrated into a liquid-crystal display. Experimental results indicate that the Si-nanocrystal photosensor has better performances in dark current and quantum efficiency than those of the p-i-n diode. The Si-nanocrystal photosensor also exhibited response linearity and speed comparable to the p-i-n diode. In terms of long-term operation and reliability, the lifetime of the Si-nanocrystal photosensor is roughly two orders longer than that of the p-i-n diode. The Si-nanocrystal ambient light sensor has considerable flexibility in the design of spectrum, geometry, and the readout circuit, which is achieved by adjusting the nanocrystal size and applying a vertical stacking structure. The Si-nanocrystal photosensor can be a promising low-cost PMOS-only solution for various photosensing applications on display panels. [ABSTRACT FROM AUTHOR]

The shallow trench isolation (STI) stress effect along the length direction on short-channel MOSFET devices has already been widely studied. However, the effect along the width direction has seldom been specifically analyzed. In this letter, we combine a novel charge-based capacitance measurement technique, which is used to extract the intrinsic CGC of MOSFET devices, and the split capacitance-voltage method to extract the mobility of devices with various channel widths. Although it is already known that under the influence of compressive STI stress along the width direction the mobility of both NMOS and PMOS devices will degrade with decreasing width, it is the first time to quantify the impact of this STI stress component on MOSFET devices. [ABSTRACT FROM AUTHOR]

In modern electronics, as the supply voltage decreases, the protection devices for low-voltage application are gaining more importance. In this paper, two types of diode-based transient voltage suppressors are proposed for protection against electrical overstress and electrostatic discharges. The modified diodes show lower leakage under low-voltage and sharp I-V transition after breakdown by only a few modifications on the fabrication process. [ABSTRACT FROM AUTHOR]

This paper presents an integrated vibration power generator system. The system consists of a mini electromagnetic vibration power generator and a highly efficient energy harvesting circuit implemented on a minute printed circuit board and a 0.35-μm CMOS integrated chip. By introducing a feedback control into the dc-dc pulsewidth modulation (PWM) boost converter with feedforward control, the energy harvesting circuit can adjust the duty ratio of the converter following the variation of the input voltage and the voltage of energy storage element to get high energy conversion efficiency. The energy harvesting circuit rectifies the input ac voltage, steps up the dc output of the rectifier by the dc-dc PWM boost converter with feedforward and feedback control and stores the electric energy into a super capacitor, which can be used as a small electrical power supply for an intelligent micro sensor network. [ABSTRACT FROM AUTHOR]

In developing a fast statistical testing methodology to predict the postcycling low-temperature data-retention lifetime of split-gate Flash memories, word-line stress is used to accelerate the charge-gain effect responsible for bit-cell-current reduction among the tail-bits. To find out the voltage dependence on data-retention lifetime, various word-line stress voltages are performed to enhance the charge-gain effect of the erase-state cells. At an accelerated state, word-line stress lifetime tests can be completed within a much shorter test period and still provide accurate lifetime prediction for embedded Flash-memory products [ABSTRACT FROM PUBLISHER]

A 10T/pixel CMOS digital pixel sensor with clock count output, ultra low supply voltage, and wide dynamic range is presented. The pixel fabricated by a standard 0.25-μm CMOS logic process comprises a reset transistor, a photo-diode, a comparator, and an inverter with pixel size of 9.4×9.4 μm2 and 24% fill factor. The amplified logarithmic output response similar to the light response of human eye is demonstrated in this work. The pixel can operate at a supply voltage as low as 1.2 V without affecting its output characteristics. The dynamic range of this cell limited by either the subsequent analog-to-digital circuit resolution or the rising and falling time of output clock is higher than 90 dB with an 8-bit resolution. [ABSTRACT FROM PUBLISHER]

In developing an accurate lifetime-prediction model for postcycling data-retention failure rate of split-gate Flash memories, a floating-gate potential extraction method from the measured bit-cell-current data is proposed. Stress-induced leakage current through the coupling oxide caused by the source-side channel hot electron injection during program operation is the major cause for postcycling data-retention failure bits. Considering charge conservation and trap-assist-tunneling leakage current, the charge-gain behavior under low-temperature bake is modeled and the failure rate under various measured conditions can be predicted precisely. We have found that data-retention lifetime decreases as program/erase (P/E) cycling increases, while failing bits increase with numbers of P/E cycling. [ABSTRACT FROM PUBLISHER]

In this work, we describe a novel operation of charge-injection-induced error-free charge-based capacitance measurement (CLEF CBCM) method. This method has the simplest test structure among various CBCM methods by using only one N/PMOS pair. CLEF CBCM has the advantage of being free from charge-injection-induced errors and of efficient layout area usage. It is very suitable for industrial applications for large amounts of accurate capacitance characterizations with a limited layout area. Besides, CLEF CBCM is also implemented for investigating the impact of floating dummy metal fills on interconnect capacitance directly from silicon data. [ABSTRACT FROM AUTHOR]

A multilevel/analog electrically erasable programmable read only memory cell fabricated by standard CMOS logic process is presented. The cell is operated by select-gate-controlled channel current induced drain avalanche hot hole for programming and hot electron for erasing. The self-convergent programming scheme proposed allows this cell to be easily adopted for the multilevel or analog storage. In addition, a compact SPICE subcircuit model of the cell has been established to facilitate cell behavior simulation with its interfacing circuits, especially for multilevel/analog nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

In this paper we present a CMOS image sensor design with a better sensitivity to low light intensity. This feature is achieved through a multi-resolution analog-to-digital converter (ADC). By doing so, the photo-electrical characteristic of a sensor cell can is finely tuned. A cost-effective architecture for realizing the required ADC is also proposed. This architecture leads to a faster conversion time as well as a smaller area. A simulation environment with post-layout accuracy is incorporated to demonstrate the advantages. It shows that a number of images can be captured more clearly than a traditional sensor. [ABSTRACT FROM AUTHOR]

Circuit reliability of class-E and class-A power amplifiers is investigated based on a newly developed degradation sub- circuit model. Measured degradation characteristics on the fabricated circuits agree well with the simulation predictions. Using this model, we have found that the class-E amplifier degrades faster than a class-A amplifier, due to a much higher stress level during switching. With a drastic decrease of PAE, a shorter lifetime is expected for a class-E amplifier. [ABSTRACT FROM AUTHOR]

A novel logarithmic response CMOS image sensor fabricated by 0.25-μm CMOS logic process is proposed. The new cell has an output voltage swing of 1 V in the targeted illumination range, which makes it less susceptible to noises in the readout system. Furthermore, the proposed new cell with in-pixel CDS control drastically reduces the fixed pattern noise in logarithmic mode CMOS APS. Comparing with a conventional pixel, a reduction of 10 times in fixed-pattern noise is demonstrated in the new logarithmic response CMOS image sensor. [ABSTRACT FROM PUBLISHER]

A high fill-factor self-buffered active pixel sensor and a tunable injection current compensation architecture for high dynamic range imager are proposed for scaled standard CMOS technology. The new cell, including a photo diode formed by n-well and p-type substrate and an one-transistor output buffer, shows enhanced characteristics in output voltage swing and sensitivity compared with conventional APS. The imager can achieve fill-factor of 55%, sensitivity of 3.4 V/sec-lux, and large output swing of 2.2 V at VDD=3.3 V for 0.25-μm CMOS technology. In addition, the proposed tunable injection current compensation architecture can improve dynamic range by as much as 40 dB and can be tailor designed to meet various application specifications. A dynamic range of up to 120 dB is projected by simulation results. Experimental results of the new structure, as well as simulated design of the circuit, are presented. [ABSTRACT FROM PUBLISHER]

An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-µm CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more than an order of magnitude. Through varying the bias conditions on the photogate, dynamic sensitivity can be obtained to increase maximum allowable illumination level. Combining the above two operation schemes, the dynamic range of this new cell can be extended by more than 20x. [ABSTRACT FROM AUTHOR]

This letter presents a new 2-bit/cell contact-gated one-time-programmable (OTP) device, which is demonstrated in a 90-nm CMOS logic process. The cell is programmed by electron injection and storage in the contact-etch-stop-layer (CESL) nitride film. A novel contact gate is introduced to serve as a select transistor, which allows the cell to exhibit good immunity against program and read disturbances. The 2-bit/cell operation is achieved by selectively injecting charges into the CESL on either side of the contact gate through channel-hot-electron operation. With a unit bit area of 13.8 F2, this nitride-based contact-gated OTP memory is highly feasible for advanced logic applications. [ABSTRACT FROM AUTHOR]

A new p-channel nitride-based one-time programmable (OTP) memory was developed for advanced-logic non- volatile-memory (NVM) applications. A 0.296-µm²/bit (~35 F²) OTP cell, i.e., 0.592 µm²/cell, with a self-aligned nitride storage node was fabricated using standard 90-nm CMOS processes and is fully independent of gate oxide for high scalability. Additionally, the ultrahigh-density OTP cell exhibits excellent retention, immunity against disturbance, and a wide on/off window under the band-to-band hot electron programming. In summary, the new p-channel OTP cell is a very promising solution for use in high-density logic NVM applications beyond the 90-nm technology node. [ABSTRACT FROM AUTHOR]

A novel one time programming (OTP) cell with a nitride-based storage has been developed for advanced programmable logic applications. This cell that is processed by pure logic process and decoupled with transistor gate oxide has a highly stable and extremely wide ON/OFF window. It exhibits a superior disturb immunity in program and read operations. In addition, a very small cell size (0.263 μm2) has been achieved using 90-nm pure CMOS logic process and is scalable in more advanced CMOS logic technologies by eliminating the constraint of transistor gate-oxide thickness. The all new OTP cell has a wide ON/OFF window and a superior writing efficiency by source-side injection programming mechanism. This novel OTP cell is a very promising programmable logic solution, with a fully CMOS-logic-compatible process below the 90-nm node. [ABSTRACT FROM AUTHOR]

A new NAND-type nonvolatile memory with a field-enhancing tip structure embedded in low-temperature polycrystalline silicon (LTPS) panel was demonstrated on a glass substrate for the first time. A thin-film transistor (TFT) metal-oxide-nitride-oxide-silicon (MONOS) device based on sequential lateral solidification crystallization with a fully depleted poly-Si channel, an oxide-nitride-oxide stack gate dielectric, and a metal gate is integrated into a NAND array. A NAND test array based on p-channel LTPS TFTs exhibits good cycling endurance and data retention properties and negligible program and read disturbance. These results strongly support the claim that this TFT-MONOS device is a promising candidate for use in embedded nonvolatile memory for system-on-panel and 3-D IC applications. [ABSTRACT FROM AUTHOR]

A body-tied FinFET bandgap engineered (BE)-silicon-oxide-nitride-oxide-silicon (SONOS) NAND Flash device is successfully demonstrated for the first time. BE-SONOS device [1] with a BE oxide-nitride-oxide barrier is integrated in the FinFET structure with a 30-nm fin width. FinFET BE-SONOS can overcome the unsolvable tradeoff between retention and erase speed of the conventional SONOS. Compared with the current floating-gate Flash devices, FinFET BE-SONOS provides both retention and erase-speed performance, while eliminating the scaling limitations and is, thus, an important candidate for further scaling of NAND Flash. [ABSTRACT FROM AUTHOR]

In this letter, charge-based capacitance measurement (CBCM) is applied to characterize bias-dependent capacitances in a CMOS transistor. Due to its special advantage of being free from the errors induced by charge injection, the operation of charge-injection-induced-error-free CBCM allows for the extraction of full-range gate capacitance from the accumulation region to the inversion region and the overlap capacitance of MOSFET devices with submicrometer dimensions. [ABSTRACT FROM AUTHOR]

A metal-oxide-nitride-oxide-polysilicon (MONOS) memory device fabricated by sequential lateral solidified (SLS) low-temperature polycrystalline silicon (poly-Si) technology on a glass substrate was investigated. The Si protrusions at grain boundaries (GBs) as a result of the SLS process can be well controlled and located along the width direction of the transistor. Protrusions at the GBs are utilized as emitting source to achieve a MONOS memory device with low operation voltage (≤ 20 V), fast program/erase time, and wide Vth, window by field-enhanced channel hot electron injection for programming and field-enhanced band-to-band tunneling-induced hot hole injection for erase. This is the first study to demonstrate a nonvolatile memory device in low-temperature poly-Si thin-film transistor (LTPS TFT) technology, which can be integrated with TFT-liquid crystal display, to reduce power consumption for mobile applications. [ABSTRACT FROM AUTHOR]

An AND-type split-gate Flash memory cell with a trench select gate and a buried n+ source is proposed. This cell, programmed by ballistic source side injection (BSSI), can provide high programming efficiency with a cell size of 5F². Furthermore, both the programming speed and the read current are enhanced by the shared select gate configuration. [ABSTRACT FROM AUTHOR]

Deals with a study which demonstrated a method of growing multiple gate oxide thicknesses below 5 nanometers using masked oxygen implantation. Device fabrication; Characteristics of the oxide and transistor used in the study; Effect of implant and anneal conditions; Conclusion.