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Accuracy and efficiency of chip placement process play a critical role in electronic packaging technology since it can determine the success ratio and throughput of chip packaging system. In this paper, a new motional chip placement process is proposed to improve the process efficiency, where the chip is placed onto the substrate with a contact velocity. However, the moving chip is also more likely to produce position drift on the anisotropic conductive adhesive, which will result in low accuracy of chip placement process. In view of this, a three-layer model considering the effect of the chip contact velocity is presented to address the dynamic behavior of chip placement process, where the geometrical dimensions and material properties of this model are included. In addition, the mechanism of motional chip placement process is uncovered, and the effects of key factors, including chip length, adhesive viscosity, and chip contact velocity on chip motion, are analyzed. The results show that the moving chip is helpful for the efficiency of chip placement process, but it also may cause low accuracy of chip placement process. Finally, in order to select appropriate key factors, the technical criteria are discussed, and the process window for reliable motional chip placement is established and verified by experiments. [ABSTRACT FROM AUTHOR]

Continuous peeling of thin chips and flexible devices from a donor to an acceptor is critical for high-efficiency roll-to-roll (R2R) manufacturing of flexible electronics. Here, we propose an R2R conformal peeling technique for the flexible device-on-substrate electronic assembly. First, a mechanical model is established for flexible multilayer structures conformed on curved surface, such as peeling blade, and the corresponding analytical solution of the interfacial shear stress and peeling stress of the adhesive layer is given. Then, the influence of material property and geometrical size of the device (Young’s modulus of different layers and thickness of various layers), the geometric shape of peeling blade (peeling radius and conformal angle), and R2R process parameters (tension and speed of substrate) are analyzed by the theoretical model and experimental test. The peelability law of delaminating devices from the substrate is established for the conformal peeling process. Finally, the design method for a peeling blade is proposed, and the core is to determine the diameter of the peeling blade. It is proofed by the peeling experiment of multilayer electronic devices in the packaging of radio-frequency identification tags. [ABSTRACT FROM AUTHOR]

Nondestructively and efficiently peeling thin chip from the adhesive tape is still one of the crucial techniques in IC packaging technology. In order to improve the process efficiency, a novel approach with the inverted ejecting mechanism and spring buffer head is proposed, where, however, the ejecting and spring forces applied at the chip for generating the interfacial crack are also more likely to resulting in the damage of chip. In view of this, an effective theoretical and finite element models are established considering the tape–adhesive–chip structure with ejecting and spring forces, and in the frame of fracture mechanics, the energy release rate is calculated and introduced to reveal effects of the spring buffer on the interfacial crack growth and chip breaking stresses. It is showed that the spring buffer is able to reduce the stress concentration on chip. Furthermore, according to the competing fracture behavior between the interfacial delamination and the chip cracking, the process window of thin chip peeling is suggested for selecting an appropriate spring coefficient and ejecting needle force. [ABSTRACT FROM AUTHOR]

With the rapid growth of the microelectronic packaging market, it is necessary to increase the throughput and reduce the cost of flip chip. Driven by these evolutions, a novel revolving-turret chip transferring (RTCT) technology is introduced to implement high-throughput flip chip packaging. The unnecessary time delays of packaging processes could be eliminated in the RTCT technology due to its parallel manner of motions. In order to analyze the packaging efficiency, the layout and movement sequence of the packaging system are studied, and a calculation model of packaging efficiency is proposed. Furthermore, the effects of the critical parameters (the horizontal and the vertical spacing of antennas and the maximum velocity and acceleration of the turret-type head) on packaging efficiency are investigated to search out the optimal parameters combination. To verify the performance of the RTCT technology under optimal parameters combination, two cases are implemented and compared. The results show that due to parallel motions of processes, unnecessary delays affecting the packaging efficiency have been reduced, and the packaging efficiency of ALN-9714 inlay could be more than 35k chips per hour. In addition, compared with the conventional flip chip packaging process, the RTCT technology is more effective in packaging the chips on antennas with multicolumn layout and small horizontal spacing. [ABSTRACT FROM AUTHOR]

The serious warpage issues of ultrathin chip-on-flex (UTCOF) assembly induced by mismatched thermal stresses have greatly affected the mechanical stability and reliability of emerging ultrathin chip packaging technology. Currently, a theoretical prediction as a convenient and straightforward approach is still lacked for describing effectively the thermal-mechanical behavior of UTCOF during the adhesive curing and cooling process. In consideration of the adhesive thickness approximating to ultrathin chip and flexible substrate thickness, we develop a layerwise-model of ultrathin chip-adhesive-flex structure under plain strain condition, where the behavior of thick adhesive bonding can be described precisely through increasing the subdivided mathematical plies. Further, the analytical results show that the concave and convex forms of ultrathin chip warpage yield at the end of the curing and cooling process respectively. Meanwhile, the effects of its structure dimensions and material properties are also revealed for discussing a way to relieve the extent of ultrathin chip warpage. Additionally, in order to verify the validity of the theoretical prediction, we also introduce the corresponding numerical technique and experimental method. These results suggest that a kind of rigid and ultrathin flexible substrate such as metal foil should be adopted for small warpage of ultrathin assembly. [ABSTRACT FROM AUTHOR]

Chip picking-up with vacuum sorption is a critical technology in flip-chip packaging for separating chip intactly from donor adhesive tape. With increasing length/thickness ratio of chips, the incomplete separation affects the success rate of this process, even leads to the failure of chips. Here, we present a theoretical model with a bisection algorithm to calculate the effective size of tape that contributes to the crack growth, and introduce an energy release rate and pick-up force to evaluate the ability of thin chip picking-up. The finite-element method with a virtual crack-closure technique is constructed to validate the established process model. The effects of the type of pick-up head, length of chip, thickness, and material of tape on chip picking-up process are also revealed to improve the ability to propagate a crack in the adhesive layer. Furthermore, the crack propagation in the adhesive layer with increasing pick-up displacement is predicted to determine the critical value of the thin chip complete separation from compliant tape. These results suggest that the thinner and more compliant tape should be adopted in the chip picking-up process. [ABSTRACT FROM PUBLISHER]

The reliable picking-up of thin chip using the vacuum sorption determines the success rate of flip chip assemblies from donor tape to receptor substrate. An analytical solution to model the chip–adhesive–tape structure with vacuum loads is introduced to understand the fracture mechanism of chip picking-up. The critical process parameters (the length of bonded region, vacuum strength, and pick-up displacement, etc.) are investigated. Theoretical predictions are used in combination with virtual crack-closure-based finite-element technique to reveal the detaching behavior between the chip and the adhesive tape. The results show that the length of the bonded region should be controlled less than 40% of chip length to eliminate the effects of chip thickness, and the higher vacuum strength acting on the adhesive tape is able to accelerate the detachment of the chip from the adhesive tape. In particular, a process window is proposed to enhance the reliability and efficiency of picking-up for a thin chip. [ABSTRACT FROM AUTHOR]