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Brain-inspired neuromorphic computing has garnered significant attention for going beyond the constraint of von Neumann architecture. To emulate the human brain functions, various artificial synaptic devices have been proposed. Due to the high reliability and the CMOS compatibility, the synaptic transistors based on charge trapping (CT) mechanism have been considered to be one of the most promising candidates. However, most of the synaptic transistors based on CT mechanism were fabricated by costly vacuum-based techniques. In this report, based on a fully solution-driven strategy, the InZnO synaptic transistors, with Nd2O3 as the CT layer and ZrO2 as the dielectric layer, were integrated. The typical synaptic behaviors, including excitatory postsynaptic current, inhibitory postsynaptic current, memory enhancement, potentiation, and depression characteristics, were simulated by modulating presynaptic spikes. It is confirmed that the fabricated synaptic transistor shows low channel conductance and low energy consumption of 0.13 pJ per synaptic event. A recognition accuracy of 93.0% was achieved for the MNIST handwritten digital image dataset by an artificial neural network simulation. This study demonstrates the feasibility of solution-processed synaptic transistors, which exhibit significant potential for the neuromorphic applications. [ABSTRACT FROM AUTHOR]

The von Neumann bottleneck is a critical limitation in synaptic devices. Therefore, artificial synaptic devices resembling biological neuromorphic synapses have been developed to overcome the von Neumann bottleneck. However, synaptic devices require voltages, which results in considerable energy consumption. Here, photonic synaptic devices with the vertical structure of indium tin oxide (ITO)/SnO2/Al2O3/CsBi3I10/Au are fabricated, which can work in the self-powered mode owing to the photovoltaic effect endowed by a vertical multilayer structure. Several fundamental synaptic functions, such as excitatory postsynaptic current, paired-pulse facilitation, short-term plasticity (STP), long-term plasticity (LTP), pulse-frequency-dependent plasticity, transition of STP to LTP, and the learning experience are emulated. Moreover, Morse-coded external light information is decoded by self-powered photonic synaptic devices. The results indicate that self-powered photonic synaptic devices based on lead-free perovskites exhibit great potential for efficient neuromorphic computing and optical wireless communication. [ABSTRACT FROM AUTHOR]

The development of large-scale manufacturing and cost-saving artificial synaptic devices is of great significance for the realization of hardware neural networks. In this work, the In2O3 synaptic transistors with boron ion-doped ZrOx as the dielectric layer were fabricated by the solution process. The large counterclockwise hysteresis indicates that the nonvolatile memory capacity of the synaptic transistors was improved by boron ions doping. Typical synaptic functions including excitatory postsynaptic current, paired pulse facilitation, and high-pass filtering properties were simulated by applying gate bias. The multilevel channel conductance can be modulated by successive positive and negative pulses. Additionally, small nonlinearities were shown in the potentiation and depression processes, and high accuracies of 92.0% (small digits) and 93.8% (large digits) were obtained in digital recognition training. This study indicates that oxide-gated synaptic transistors based on the boron ions doping strategy show great potential for neuromorphic applications. [ABSTRACT FROM AUTHOR]

With the popularization of electronic devices and the demand for portability, low-power consumption has become crucial for integrated circuit chips. Two-dimensional (2D) semiconductors offer significant potential in constructing low-power devices due to their ultrathin thickness, enabling fully depletion operation. However, fabricating these 2D low-power devices, such as negative-capacitance transistors or tunneling transistors, often requires multiple layers of gate dielectrics or channel band engineering, adding complexity to the manufacturing process and posing challenges for their integration with silicon technology. In this work, we have developed low-power MoS2 metal–semiconductor field effect transistors utilizing a standard metal–semiconductor contact, which eliminates the need for gate dielectrics and semiconductor heterojunctions. It demonstrates a sharp subthreshold slope (SS ∼ 64 mV/dec), a minimum operating gate voltage range (−0.5 ∼ 1 V), a minimum current hysteresis (3.69 mV), and a stable threshold voltage close to 0 V (Vth ∼ −0.27 V). Moreover, we implemented an inverter circuit with a high voltage gain of 47. [ABSTRACT FROM AUTHOR]

As one of the most important members of the two-dimensional (2D) chalcogenide family, MoS2 plays a fundamental role in the development of 2D electronic and optoelectronic designs. However, MoS2-based optoelectronic devices are hindered by their weak light–matter interactions, which make it challenging to achieve excellent device performance in photoelectronic memory applications. Here, we developed a multifunctional optoelectronic memory by coupling Au nanoparticles with MoS2, where the presence of Au nanoparticles on the surface significantly enhanced the light absorption capacity of MoS2 through the surface-plasmon-enhanced effect. The device achieved a photoresponse capability with a light current-to-dark current ratio exceeding 103, surpassing the majority of values reported for comparable photoconductive detectors. Importantly, it exhibits excellent light writing, storage, and erasuring capabilities, with a storage time exceeding 1000 s. Based on this device, a 3 × 3 array hardware core is designed to mimic human retinal imaging under the irradiation of 660, 532, and 457 nm lasers by using R-CNN algorithm, reducing power consumption, and redundancy. These advancements have the potential to drive future developments in neuromorphic electronics, particularly in optical information sensing and learning. [ABSTRACT FROM AUTHOR]

The integration of data storage and computing capabilities into a single physical component has led to the development of a microneuronal network system with high precision and speed rates. To achieve this system architecture, bold innovations in the underlying hardware structure and neural network architecture are required. This article introduces an optoelectronic storage device based on the MoS2/h-BN/graphene van der Waals heterojunction transistor. At room temperature, the transistor exhibits an electron mobility of up to 340 cm2/(V·s) and a large storage window due to its unique van der Waals heterojunction. The transistor's reconfigurable nonvolatile optoelectronic properties enable the construction of logic gates, including "AND", "OR", "NAND", and "NOR". Leveraging these logic gates, a microneural network system is created that simulates future machine vision applications. The system achieves a remarkable recognition rate of 96.3% for images in a multidimensional color space, demonstrating the significant development potential of the microneural network system based on the MoS2/h-BN/graphene vdW heterojunction transistor in future machine vision. [ABSTRACT FROM AUTHOR]

α-Synuclein (α-Syn) is a major biomarker of Parkinson's disease (PD). Concentration detection of α-Syn in cerebrospinal fluid and plasma of patients are used as a clue for early PD detection. Herein, we propose a thin-film transistor (TFT) biosensor based on an indium gallium zinc oxide (IGZO) thin film fabricated by the sol-gel method. The IGZO TFT biosensor is used for the early detection of PD after surface functionalization for α-Syn. The surface functionalization worked on the surface of the extended gate indium tin oxide sensing platform instead of the channel layer of TFT. Depending on concentrations of α-Syn in human cerebrospinal fluid and plasma, we diluted six different concentrations of α-Syn for detection, ranging from 1 pg ml−1 to 100 ng ml−1. The result shows that the biosensor exhibits high sensitivity and selectivity for α-Syn, a reliable sensing performance with a sensitivity of 189.9 mV dec−1, and a coefficient of determination R2 of 99.7% between 10 pg ml−1 and 100 ng ml−1. [ABSTRACT FROM AUTHOR]

Massive data processing with high computing efficiency and low operating power is required owing to the rapid development of artificial intelligence and information technology. However, the von Neumann structure computing system with the separated memory and processor can cause large energy consumption and a low running speed during massive data processing. Therefore, the brain‐inspired neuromorphic computing system is developed, that can provide hardware support for emulating biological synaptic functions and realizing highly intensive data processing with low power consumption. As a neuromorphic device, the optoelectronic synaptic device (OSD) is regarded as an ideal device to replace the von Neumann‐based computer because of its ultrafast signal transmission, large bandwidth, low energy consumption, and wireless communication. Owing to their unique optoelectronic property, metal halide perovskites (MHPs) have received growing attention as effective photosensitive materials in OSDs. Therefore, the review introduces the recent progress on OSDs based on MHPs (MHPs‐OSDs) including the structures and properties of MHPs, and the architectures and performance characteristics of MHPs‐OSDs. Furthermore, applications of MHPs‐OSDs are presented. Finally, the outlook and opportunity of MHPs‐OSDs are discussed. [ABSTRACT FROM AUTHOR]

In this work, In2O3 nanofibers were fabricated by electrospinning, and a field effect transistor (FET) based on In2O3 nanofibers was integrated. A hydroxyl-assisted strategy was proposed for both stability and performance enhancement for the FET. Hydrogen peroxide (H2O2) was added into a precursor solution for electrospinning. It is found that the stability of the FET is improved after H2O2 incorporation, while the mobility is decreased. Surprisingly, after UV irradiation, the FET with both high mobility and high stability was obtained. It is assumed that under UV irradiation, H2O2 is decomposed into highly reactive hydroxyl radicals (•OH), which contributes to the degradation of the polymer. XPS and FT-IR analysis verify that oxygen- and carbon-related defects can be removed through the hydroxyl-assistant strategy. Furthermore, the flexible FET based on In2O3 nanofibers with H2O2 addition and UV irradiation was fabricated on the PI substrate, and the high electrical performance is further demonstrated. This strategy makes it possible to fabricate the oxide nanofiber FET with both high mobility and high stability. [ABSTRACT FROM AUTHOR]

Electrolyte-gated synaptic transistors are promising for artificial neural morphological devices. However, few literatures have been reported regarding the manufacturing of electrolyte-gated synaptic transistors with low cost and biocompatible components. Here, the fully transparent synaptic transistors based on water-induced In2O3 thin films have been integrated by sol–gel method at low temperature, and lactose dissolved in citric acid solution is used as the gate electrolyte. The migration of the ions at the interface plays a crucial role in the potentiation and depression of the synaptic weight. In this work, the biological synaptic functions, including excitatory postsynaptic current, paired-pulse facilitation, high-pass filtering characteristics, short-term memory, and long-term memory, are mimicked. Meanwhile, based on the potentiation/depression behaviors of the synaptic transistor, a three-layer artificial neural network is applied for pattern recognition, and the recognition accuracy is as high as 94.6%. This study offers a possibility to realize fully transparent synaptic devices with biocompatible components at low temperature. [ABSTRACT FROM AUTHOR]

The formation of Ohmic contact between metal electrode and 2D semiconductor channel is considered a key factor for performance improvement of 2D metal–oxide–semiconductor field‐effect transistors (MOSFET). However, the Schottky barrier at the metal electrode/2D semiconductor interfaces cannot be lowered effectively due to the pinning effect of Fermi levels, which makes it hard to obtain lower Ohmic contact resistance. Until now, although physical transfer metal electrode or inserted tunneling layer has been reported to get rid of the Fermi‐level pinning effect, these different designs of electrode engineering are not systematically compared. To serve better Ohmic contact, three different designs of electrode engineering are employed in 2D MoS2 MOSFET: evaporating Ag electrode on MoS2, transferring MoS2 to Ag electrode, and inserting ultrathin AlOx tunneling layer. Our experimental results demonstrate that the transferring MoS2 to Ag electrode in 2D MoS2 MOSFET can obtain the lowest contact resistance and Schottky barrier of 0.45 Ωcm and 12.8 meV, respectively. On this basis, photodiodes with obvious rectifying behavior are fabricated using schemes of electrode engineering, due to their different Schottky barrier high. The detailed contrastive analysis in our three different designs of electrode engineering can provide valuable guidance to optimize the performance of 2D semiconductor MOSFET. [ABSTRACT FROM AUTHOR]

Emulating synaptic behavior using the three-terminal and ion-coupled transistors is considered as a promising strategy for the realization of neuromorphic devices. Meanwhile, one-dimensional (1-D) nanostructures show great potential for the fabrication of flexible electronic devices. In this work, 1-D indium oxide (In2O3) nanofibers were fabricated by the electrospinning (ES), and the flexible and compatible synaptic transistor based on In2O3 nanofibers was integrated on polyimide (PI) substrate. The synaptic behaviors, such as the short-term plasticity (STP) and long-term plasticity (LTP), are simulated by the synaptic transistor with chitosan solution as the gate dielectric. The fabricated synaptic transistor exhibits good biocompatibility and environmental compatibility, and the pattern recognition rate of the simulated device array by the Mixed National Institute of Standards and Technology (MNIST) database of the handwritten digits is confirmed to be as high as 92%. [ABSTRACT FROM AUTHOR]

Relative humidity (RH) in storage environment has a great impact on the electrical performance of thin film transistors (TFTs), and the RH is critical for semiconductor manufacturing and device packaging. In this work, solution-processed indium oxide (In2O3) TFT is fabricated, and the electrical performance of the device is investigated after being exposed to various RH conditions. It is found that the threshold voltage (Vth) and the mobility of In2O3 TFT exhibit clear responses to the RH ranging from 23% to 85%. The inherent mechanism about the humidity effect on the electrical performance is elaborated, and this is due to the "donor effect" from the absorbed water molecules. In addition to the effect on Vth and mobility, RH also exhibits a significant effect on the electrical stability of the TFT. The experimental result indicates that the In2O3 TFT exposed to RH <50% exhibits excellent stability with an applied positive bias stressing for 2000s. [ABSTRACT FROM AUTHOR]

Thin-film transistors (TFTs) with bilayer channels were used to improve the field-effect mobility and bias stress stability of the TFTs. Homogeneous structures were fabricated by the combination of a carrier deficient layer made of In2O3 thin film annealed in oxygen atmosphere (InO:O) and an electron injection layer made of In2O3 thin film annealed in air (InO:A). Compared with the InO:A/InO:A TFT with only air annealing, the field-effect mobility of InO:O/ InO:A TFT with two-step annealing process was improved from 0.04 to 5.11 cm2/Vs, the on/off current ratio was ameliorated from 4.6 × 105 to 7.6 × 107 A, while the VTH is decreased from 12.5 to 4.7 V under the positive bias stressing (PBS). It is confirmed that the excessive oxygen vacancies are produced by annealing the thin film in the air. The electrical performance of the InO:O/InO:A TFTs with two-step annealing process is greatly improved due to the formation of a low defect state and high carrier concentration electron transport layer, through the combination of the carrier transport layer and the carrier injection layer. These optimized electrical properties indicate an important step toward achieving transparent, high performance, and low-temperature metal oxides TFTs. [ABSTRACT FROM AUTHOR]

For field effect transistors (FETs) based on electrospun oxide nanofibers, the electrical stability can be deteriorated by high-temperature annealing treatment. In this work, the self-passivation of an In2O3 nanofiber FET is achieved by the consequent thermal treatment, water treatment, and deep ultraviolet (DUV) irradiation, and the FET is named as a TWD (thermal treatment-water treatment-DUV irradiation)-device. For comparison, the devices treated by thermal treatment and by thermal + water treatment were also fabricated and abbreviated as a T-device and a TW (thermal treatment-water treatment)-device, respectively. From the transfer characteristics of the T-, TW-, and TWD-devices, the electrical performance is first degraded by water treatment and then recovered after DUV irradiation. The positive bias stress test confirms the stability enhancement after TWD treatment, indicating the achievement of the self-passivated FET based on In2O3 nanofibers. The excellent electrical stability is owing to the structural relaxation and the removal of trap sites such as oxygen vacancy and hydroxide. Integrated with the high-k ZrO2 dielectric, the TWD-In2O3/ZrO2 FET exhibits further improved electrical performance, including a mobility of 3.35 cm2/V s and a high on/off current ratio of 107. [ABSTRACT FROM AUTHOR]

In this report, In2O3 nanofiber networks (NFNs) were prepared by electrospinning and the field-effect transistors (FETs) based on In2O3 NFNs were fabricated. The effects of plasma treatment on the electrical performance of the FETs based on In2O3 NFNs were investigated. It is found that the oxygen vacancy in In2O3 NFNs can be tuned by the plasma treatment and the electrical performance of the FETs can be tuned accordingly. In this work, X-ray photoelectron spectroscopy was employed to investigate the chemical stoichiometry in In2O3 nanofibers with respect to plasma treatment conditions. The electrical performances of the FETs based on In2O3 NFNs treated by various plasma treatment conditions were systematically studied. It is found that, compared to those without O2 plasma treatment, the FET based on In2O3 NFNs treated by O2 plasma at 120 W for 5 min exhibits high electrical performance, including the variation of threshold voltage from −22.34 to 7.81 V and current on/off ratio from $\sim 10^{{3}}$ to $\sim 10^{{7}}$ and a $\mu _{\text {FE}}$ of 1.51 cm2 /Vs. This result demonstrates that moderate plasma treatment can be adopted to improve the electrical performance of the FETs based on metal oxide NFNs. [ABSTRACT FROM AUTHOR]

A binary ultra‐wideband multiple‐input‐multiple‐output (MIMO) antenna is proposed and fabricated. In order to increase the impedance bandwidth and resonance frequency, U‐shaped branches, defected ground structure, folded stepped impedance stubs, and window‐shaped radiation patch slots are analyzed. The total size of the MIMO antenna is 80 mm × 35 mm, and the measured relative impedance bandwidth realizes 131% (2.57‐12.2 GHz). Without the addition of a decoupling structure and a metal isolation bar, the isolation measured by this work is less than −15 dB. The measured antenna gain is between 3.064 and 4.669 dBi. The measured envelope correlation coefficient value is less than 0.005, and diversity gain is almost equal to 10 dB. The channel capacity loss obtained in the measurement is less than 0.4 bit/s/Hz in the bandwidth except for 9 to 10 GHz. Excellent properties make it suitable for modern wireless communication applications. [ABSTRACT FROM AUTHOR]

One-dimensional metal-oxide nanowire networks (NNs) are considered as important elements in electronics due to their unique physical and electrical performances. In this letter, Sn1-x Gax O NNs were fabricated and field-effect transistors (FETs) based on Sn1-x Gax O NNs with different Sn/Ga ratios were constructed. The characteristics of the FETs have been systematically investigated. In order to promote the adhesion and electrical performance of nanowires, Sn1-x Gax O NNs were welded by introducing the polymer mixture containing poly vinyl pyrrolidone and poly methyl methacrylate. Utilizing a welding process, the transport properties of Sn1-x Gax O NNs have been greatly promoted, and the FETs based on Sn0.8 Ga0.2 O NNs exhibit optimum electrical performance. Once integrated with high-k ZrOx dielectric, the FET based on Sn0.8 Ga0.2 O NNs/ZrOx exhibits high stability and high electrical performance, including $\text{a}\mu _{\text{FE}}$ of 5.2 cm2 /V s, an $\text{I}_{\text{on}} /\text{I}_{\text{off}}$ of $1.5\times 10 ^{6}$ , a subthreshold voltage of 170 mV/decade, an on voltage of −0.25 V, and a negligible hysteresis of ~0.12 V. The successful fabrication of the FETs based on Sn0.8 Ga0.2 O NNs lays the foundation for the development of low-consumption, low-cost and high-performance electronic devices. [ABSTRACT FROM AUTHOR]

Surface plasmon is promising for applications in 2-D semiconductor photodetector due to their great potential to improve light absorption of 2-D semiconductor, where the poor light absorption of 2-D semiconductor limits the performance of 2-D photodetector to some extent. However, high-energy deposition processes of metal surface plasmon damage the surface crystal lattice of 2-D semiconductor, which hampers the current transport in 2-D semiconductor. Here, we report the cladded surface-plasmon-enhanced black-phosphorus (BP) photodetector with damage-free metal–semiconductor interface. Without the adverse effect of the direct deposition process for metal surface plasmon, the cladded surface-plasmon-enhanced BP photodetector exhibits a superior photoresponse enhancement by up to 1000%, which exceeds other conventional surface-plasmon-enhanced 2-D semiconductor photodetectors. Our results provide guidelines to design advanced surface-plasmon-enhanced 2-D semiconductor photodetector for practical application. [ABSTRACT FROM AUTHOR]

Although plenty of two-dimensional (2D) semiconductor heterostructure photodetectors have been studied, there is still a lack of systematic comparison and analysis about photovoltaic and photoconductive 2D semiconductor photodetectors. Taking advantage of the 2D semiconductor van der Waals heterostructure, this work constructs a photovoltaic (PV) GeSe/MoS2 and a photoconductive (PC) GeSe/graphene photodetector, respectively. The PC GeSe/graphene photodetector achieves relatively higher photoresponsivity (R), where R can reach up to 104 AW−1. The PV GeSe/MoS2 photodetector, by contrast, obtains a faster photoresponse speed. More importantly, the photoresponse properties of the PV GeSe/MoS2 photodetector can remain constant under the reverse bias, due to the minority carrier conduction in its depletion region at this time. The different characteristics of the two type 2D photodetectors are explored in detail, which can play a guiding role in the construction of high-performance photodetectors. [ABSTRACT FROM AUTHOR]

In this letter, the water-induced (WI) In2O3 nanofibers were prepared by electrospinning using poly(vinyl alcohol) as polymer. The field effect transistors (FETs) based on In2O3 nanofibers were integrated, and the annealing dependence of the FETs performance was investigated. It is found that the FET based on WI In2O3 nanofibers annealed at 380 °C for 1 h (In2O3 -380-1h) exhibits a field-effect mobility ($\mu _{{\text {FE}}}$) of 1.53 cm2/Vs, and an ON/ OFF current ratio ($\text{I}_{{ \mathrm{\scriptscriptstyle ON}}}/\text{I}_{{ \mathrm{\scriptscriptstyle OFF}}}$) of $\sim {8}\times {10}^{{{4}}}$. Interestingly, the electrical performance of the FET based on WI In2O3 nanofibers annealed at 280°C for 10 h (In2O3 -280-10h) is comparable with the FET based on In2O3 -380-1h. To further improve the electrical performance of the FETs processed at low temperature, the FET based on In2O3 -280-10h as the channel and the aqueous-route derived ZrOx as dielectric was integrated. The optimized FET exhibits a $\mu _{{\text {FE}}}$ of 5.8 cm2/Vs, an $\text{I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ of ~107, and a subthreshold swing (SS) of 150 mV/decade. This nontoxic and fully water-inducement approach is highly expected for the fabrication of low-temperature and flexible circuitry. [ABSTRACT FROM AUTHOR]

Transparent oxide semiconductors exhibit great potential as fundamental building blocks for electronic applications. However, the lack of high‐performance p‐type oxide materials limits their potential applications for transparent electronics. Ternary p‐type perovskite NdAlO3 thin films are prepared by spin coating and annealed at various temperatures. It is demonstrated that neodymium vacancies (VNd) is generated in NdAlO3 thin film, and the presence of VNd results in high hole mobility. The thin‐film transistors (TFTs) based on NdAlO3 thin film are integrated and exhibit typical p‐channel transistor behavior. The TFT based on NdAlO3 thin film annealed at 700 °C exhibits an optimized electrical performance, including a field‐effect mobility (µFE) of 0.19 cm2V−1s−1 and an on/off current ratio (Ion/Ioff) of ≈105. When high‐k Al2O3 dielectric is integrated into the TFTs, the µFE and Ion/Ioff are further improved to 9.93 cm2V−1s−1 and ≈106, respectively. The fabrication of a p–n junction based on p‐NdAlO3/n‐In2O3 heterojunction further confirms the excellent p‐type performance of the perovskite NdAlO3 thin films. This work not only demonstrates the possibility of p‐type perovskite NdAlO3 thin films applicable for transparent electronics, but also provides guidelines for the design of novel p‐type oxide semiconductors. [ABSTRACT FROM AUTHOR]

Since graphene has been successfully exfoliated, two-dimensional (2D) materials constitute a vibrant research field and open vast perspectives in high-performance applications. Among them, bismuthene and 2D bismuth (Bi) are unique with superior properties to fabricate state-of-the-art energy saving, storage and conversion devices. The largest experimentally determined bulk gap, even larger than those of stanene and antimonene, allows 2D Bi to be the most promising candidate to construct room-temperature topological insulators. Moreover, 2D Bi exhibits cyclability for high-performance sodium-ion batteries, and the enlarged surface together with the good electrochemical activity renders it an efficient electrocatalyst for energy conversion. Also, the air-stability of 2D Bi is better than that of silicene, germanene, phosphorene and arsenene, which could enable more practical applications. This review aims to thoroughly explore the fundamentals of 2D Bi and its improved fabrication methods, in order to further bridge gaps between theoretical predictions and experimental achievements in its energy-related applications. We begin with an introduction of the status of 2D Bi in the 2D-material family, which is followed by descriptions of its intrinsic properties along with various fabrication methods. The vast implications of 2D Bi for high-performance devices can be envisioned to add a new pillar in energy sciences. In addition, in the context of recent pioneering studies on moiré superlattices of other 2D materials, we hope that the improved manipulation techniques of bismuthene, along with its unique properties, might even enable 2D Bi to play an important role in future energy-related twistronics. [ABSTRACT FROM AUTHOR]

Electrospinning technique is considered to be one of the most powerful approaches for the preparation of one-dimensional (1D) metal oxide nanofiber networks (NFNs). In this report, In2O3 NFNs were fabricated by electrospinning using polymethyl methacrylate (PMMA) as polymer and epoxy resin as additive. Benefiting from the excellent chemical properties of PMMA, In2O3 NFNs with impact stacking were prepared at a relatively low annealing temperature by a welding process. The welded In2O3 NFNs were characterized by various techniques and the electrical performance of the field-effect transistors (FETs) based on the welded In2O3 NFNs were systematically investigated. It is observed that the FET based on In2O3 NFNs annealed at 320 °C, with a nanofiber density of $0.4\,\,\mu \text{m}^{-{1}}$ exhibits high electrical performance, including an ${I}_{ {\mathrm{{ON}}}}/{I}_{ {\mathrm{{OFF}}}}$ of $\sim {5}\times {10}^{{7}}$ , a $\mu _{\text {FE}}$ of 1.27 cm2/V s, an on voltage of −8 V and a hysteresis of 5 V. A device array with ${4}\times {5}$ units was fabricated and tested, confirming the excellent reliability and reproducibility of the FET. [ABSTRACT FROM AUTHOR]

In this letter, high-performance thin-film transistors (TFTs), with indium oxide (In2O3) as front channel layer, high permittivity ZrO2 as dielectric layer, and aluminum oxide (Al2O3) as passivation layers were integrated by a fully solution process. It is found that the incorporation of Al2O3 passivation layer gives rise to a sharp decrease in the off current (Ioff) and a corresponding increase in the on/off current ratio ($\text{I}_{\text {on}}$ /Ioff) of the TFTs, compared to that without Al2O3 passivation. Furthermore, the thickness effect of the passivation layer on the performance of In2O3 /ZrO2 TFTs has been investigated systematically. The In2O3 /ZrO2 TFTs with optimized Al2O3 passivation layers can be operated at 3 V with high performance, including a high field-effect mobility of 21.22 cm2 /V s, a large $\text{I}_{\text {on}}$ /I off of 107 and a negligible hysteresis (~0V). This work demonstrates an effective strategy for the construction of high performance TFTs by incorporating the passivation layer. [ABSTRACT FROM AUTHOR]

Emulating the essential synaptic working principles using a three-terminal synaptic transistor has been an important research field in recent years. Electrospun metal oxide nanofibers have been regarded as promising blocks for large-area, low-cost, and one-dimensional (1D) electronic devices. In this letter, zinc-tin oxide (ZnSnO) nanofibers were fabricated by electrospinning, and the synaptic transistors based on ZnSnO nanofibers were integrated. To mimic the synaptic behavior of human brain, LiClO4 dissolved in polyethylene oxide was used as the gate electrolyte in the synaptic transistors. The plasticities, including short term and long term, are mimicked with the help of electrolyte ion dynamics under low and large bias voltage, and an energy consumption of as low as 0.44 pJ per event is observed. This work demonstrates a new approach for establishing the large-scale, energy-efficient 1D artificial synapses for neuromorphic networks. [ABSTRACT FROM AUTHOR]

Recently, p-type metal–oxide–semiconductors have attracted considerable interests for the applications in optoelectronic devices and low-power complementary metal–oxide–semiconductor circuits. In this report, ternary p-type CuAlxOy semiconductor thin films were fabricated by sol–gel method and integrated as channel layers in thin-film transistors (TFTs). The electrical performances of CuAlxOy TFTs, together with the characteristics of CuAlxOy thin films (e.g., crystalline phases, chemical compositions, surface morphology, and optical transmittances), were systematically studied at various annealing temperatures (${T}_{a}$). The phase-pure CuAlO2 thin films were obtained at ${T}_{a}$ above 800° C in N2 atmosphere. CuAlO2 TFTs annealed at 900 ° C based on high-k Al2O3 exhibited optimized electrical performance, including a hole mobility of 1.36 cm2/Vs and on/off current ratio of $\sim 1 \times 10^{\textsf {5}}$. This paper not only demonstrates the successful fabrication of high-quality p-type CuAlO2 semiconductor thin film and electronic devices by sol–gel process but also provides guidelines for related ternary p-type oxide semiconductor material and device performance improvements. [ABSTRACT FROM AUTHOR]

Abstract: The fabrication of functionalized 1D oxide fibers with accurate control of orientation, location, and number is highly demanded and challengeable based on current techniques, which hinder their practical application in opto/electronic devices. Herein, a rapid and simple method is developed to directly draw the oxide fibers from its polymer solution over large area. The draw‐spinning method enables the accurate positioning of individual fiber and the construction of complex patterns, holding great potentials in fiber‐based electronics. The assembled field‐effect transistors (FETs) based on single indium oxide (In2O3) fiber exhibit excellent current modulation capability with a high on/off current ratio of 106. Adjusting the number of fibers within the channel, the device performance can be modulated. Moreover, the draw‐spinning technique is applied to fabricate highly aligned fiber arrays by using brush pen. The FETs based on aligned In2O3 fiber arrays exhibit superior current‐driven capability compared with the devices with limited number of fibers. Their further integrations on high‐permittivity dielectric layer show improved device performance at an operating voltage of 4 V. This method is scalable and can be implemented easily to fabricate various functional fibers in both laboratory and industrial manufacturing. [ABSTRACT FROM AUTHOR]

One-dimensional metal oxide nanofibers have been regarded as promising building blocks for large area low cost electronic devices. As one of the representative metal oxide semiconducting materials, In2O3 based materials have attracted much interest due to their excellent electrical and optical properties. However, most of the field-effect transistors (FETs) based on In2O3 nanofibers usually operate in a depletion mode, which lead to large power consumption and a complicated integrated circuit design. In this report, gadolinium (Gd) doped In2O3 (InGdO) nanofibers were fabricated by electrospinning and applied as channels in the FETs. By optimizing the doping concentration and the nanofiber density, the device performance could be precisely manipulated. It was found that the FETs based on InGdO nanofibers, with a Gd doping concentration of 3% and a nanofiber density of 2.9 μm−1, exhibited the best device performance, including a field-effect mobility (μFE) of 2.83 cm2/V s, an on/off current ratio of ∼4 × 108, a threshold voltage (VTH) of 5.8 V, and a subthreshold swing (SS) of 2.4 V/decade. By employing the high-k ZrOx thin films as the gate dielectrics in the FETs, the μFE, VTH and SS can be further improved to be 17.4 cm2/V s, 0.7 V and 160 mV/decade, respectively. Finally, an inverter based on the InGdO nanofibers/ZrOx FETs was constructed and a gain of ∼11 was achieved. [ABSTRACT FROM AUTHOR]

In this study, transparent p-type CuCrxOy semiconductor thin films were fabricated using spin coating and integrated as channel layers in thin-film transistors (TFTs). The structural, morphological components, and optical properties of CuCrxOy thin films, together with device performance, were systematically investigated. The phase conversion from a mixture of CuCr2O4 and CuO to pure CuCrO2 was achieved when the annealing temperature (Ta) was higher than 700 °C. The electrical performance of the CuCrxOy TFTs on SiO2 dielectric is improved with increasing Ta from 500 °C to 800 °C. The optimized CuCrO2 TFT exhibits an on/off current ratio of ∼105 and a hole mobility of 0.59 cm2 V−1 s−1, which is much better than those previous works on solution-processed binary CuxO TFTs. To our best knowledge, this work demonstrates the ternary p-type CuCrO2 TFTs fabricated via a low-cost solution process for the first time, which represents an important advancement towards the development of all-oxide, low-cost p–n junctions and CMOS logic circuits. [ABSTRACT FROM AUTHOR]

Abstract: Although significant progress has been made towards using ZnO nanofibers (NFs) in future high‐performance and low‐cost electronics, they still suffer from insufficient device performance caused by substantial surface roughness (i.e., irregularity) and granular structure of the obtained NFs. Here, a simple one‐step electrospinning process (i.e., without hot‐press) is presented to obtain controllable ZnO NF networks to achieve high‐performance, large‐scale, and low‐operating‐power thin‐film transistors. By precisely manipulating annealing temperature during NF fabrication, their crystallinity, grain size distribution, surface morphology, and corresponding device performance can be regulated reliably for enhanced transistor performances. For the optimal annealing temperature of 500 °C, the device exhibits impressive electrical characteristics, including a small positive threshold voltage (Vth) of ≈0.9 V, a low leakage current of ≈10−12 A, and a superior on/off current ratio of ≈106, corresponding to one of the best‐performed ZnO NF devices reported to date. When high‐κ AlOx thin films are employed as gate dielectrics, the source/drain voltage (VDS) can be substantially reduced by 10× to a range of only 0–3 V, along with a 10× improvement in mobility to a respectable value of 0.2 cm2 V−1 s−1. These results indicate the potential of these nanofibers for use in next‐generation low‐power devices. [ABSTRACT FROM AUTHOR]

In this paper, high-k strontium oxide (SrOx) dielectric thin films were fabricated using simple and low-cost solution process. The formation and properties of SrOx thin films annealed at various temperatures (400 °C, 500 °C, 600 °C, and 700 °C) were investigated using numbers of characterization techniques. The electrical analysis indicates that the insulating properties of SrOx thin films were improved with increasing annealing temperature. The post-annealing at temperatures higher than 400 °C enables the SrOx thin film, exhibiting low-leakage current density of ~10−8 A cm−2 at 3 V and the areal capacitance larger than 350 nF cm−2 at 20 Hz. To further explore the possible applications of solution-processed high-k SrOx thin films for thin-film transistors (TFTs), the indium oxide (In2O3) TFTs based on SrOx thin films were integrated for testing. The optimized In2O3/SrOx TFT exhibits high performance with an average field-effect mobility of 5.61 cm2 V−1 s−1, a small subthreshold swing of 110 mV dec−1, and a large on/off current ratio of 107. To demonstrate the potential of In2O3/SrOx TFT toward more complex logic applications, the unipolar inverter was further constructed and exhibited a high gain of 9.7. Importantly, all these device parameters were obtained at an ultralow operating voltage of 3 V, which represents a step toward portable, battery-driven, and low-power consumption electronics and circuits. [ABSTRACT FROM PUBLISHER]

Solution-processed n-type oxide semiconductors have received great interest in thin-film transistor (TFT) applications. However, solution-processed p-type oxide semiconductors are not as successful as their n-type counterparts because of the lack of material choice and their complicated fabrication procedures. In this study, a simple one-step synthetic method was employed to fabricate a p-type Cu2O thin film via in-situ reaction of a CuI film in aqueous NaOH solution at room temperature. The structure, morphology, and component variations as a function of annealing conditions (≤350 °C) were investigated. The analysis indicates that the phase evolution of Cu2O → Cu2O + CuO → CuO occurred at higher temperatures and the pure CuO phase was achieved at 250 °C. The crystallinity, average grain size, and surface morphology of the CuxO thin films were found to increase in slope as the annealing temperature increased. To explore the possible applications of the obtained CuxO films as semiconducting channel components, bottom-gated TFTs on SiO2 gate dielectrics were constructed and examined. The hole mobility of the optimized device was calculated to be 0.32 cm2 V−1 s−1, along with an on/off current ratio of 5 × 104, and a subthreshold swing of 1.1 V dec−1. The further integration of the CuxO film on an Al2O3 high-k dielectric achieves an improved device performance at 2.5 V. This work successfully demonstrates a simple method to fabricate p-type Cu-based thin films and TFTs via a solution route, which represents a great step towards the development of low-cost and all-oxide complementary metal oxide semiconductor electronics. [ABSTRACT FROM AUTHOR]

Solution‐processed oxide semiconductor and dielectric thin films have been widely studied for achieving flexible, high‐performance, and low‐power electronics and circuits. In this report, high‐k HfO2 dielectrics and amorphous ZnSnO (ZTO) semiconductors are synthesized via a simple and facile redox reaction by introducing perchloric acid (HClO4, PA) as oxidizer to eliminate the Cl residuals. Thermogravimetric analysis indicates that the thermal decomposition of PA‐involved HfCl4(PA‐HfO2) xerogel is completed at 350 °C, whereas the decomposition temperature of pristine HfCl4 xerogel is higher than 450 °C. The optical, structural, morphological, compositional, and electrical properties of PA‐HfO2 and the pristine HfO2 dielectric films are investigated systematically. Meanwhile, by using chloride elimination reaction, PA‐ZTO semiconducting thin films are fabricated at various temperatures and their applications in thin‐film transistors (TFTs) are examined. Furthermore, the optimized PA‐ZTO channel layer is fabricated on PA‐HfO2 dielectric. The resulting device exhibits high electrical performance and operational stability at a low voltage of 2 V, including high saturation mobility of 13.2 cm2 V−1 s−1, small subthreshold slope of 70 mV dec−1, current ratio of 108, and threshold voltage shift of 0.05 V under positive bias stress for 3000 s. Finally, a low‐voltage resistor‐loaded inverter is built using PA‐ZTO/PA‐HfO2 TFT, exhibiting a linear relationship between supplied voltage and gain voltage and a maximum gain of 11 at 2.5 V. [ABSTRACT FROM AUTHOR]

The fabrication of water-induced amorphous high-k zirconium oxide (ZrOx) dielectrics has been proposed with the objective of achieving high performance and reducing costs for next generation displays. In this study, the as-prepared ZrOx thin films were fabricated by a sequential process, including a UV-assisted photochemical treatment and a thermal annealing process at temperatures lower than 300 °C. It is observed that the leakage current density of ZrOx thin films decreases, and the capacitance increases with increasing annealing temperatures. To verify the application possibilities of ZrOx thin films as gate dielectrics in complementary metal-oxide semiconductor (CMOS) electronics, both n-type In2O3 and p-type NiOx channel layers were integrated with ZrOx dielectrics and their corresponding electrical performances were examined. The In2O3/ZrOx thin film transistor (TFT) annealed at 250 °C exhibited a high electron mobility of 10.78 cm2 V−1 s−1, a small subthreshold swing of 75 mV dec−1, and a large on–off current ratio (Ion/Ioff) of around 106, respectively. Moreover, the p-type NiOx/ZrOx TFT exhibited an Ion/Ioff of 105 and a hole mobility of 4.8 cm2 V−1 s−1. It is noted that both n- and p-channel oxide TFTs on ZrOx could be operated at voltages lower than 4 V. The low-temperature fabrication process marks a great step towards the further development of low-cost, all-oxide CMOS electronics on flexible substrates. [ABSTRACT FROM AUTHOR]

Although there are a few research studies on solution-processed p-channel oxide thin-film transistors (TFTs), the strict fabrication conditions and the poor electrical properties have limited their applications in low-power complementary metal oxide semiconductor (CMOS) electronics. Here, the application of the polyol reduction method for processing p-type CuxO and NiOx channel layers and their implementation in TFT devices are reported. The optimized CuxO and NiOx TFTs were achieved at low annealing temperatures (∼300 °C) and exhibited decent electrical properties. Encouraged by the inspiring results obtained on SiO2/Si substrates, the TFT performance was further optimized by device engineering, employing high-k AlOx as the gate dielectric. The fully solution-processed NiOx/AlOx TFT could be operated at a low voltage of 3.5 V and exhibits a high hole mobility of around 25 cm2 V−1 s−1. Our work demonstrates the ability to grow high-quality p-type oxide films and devices via the polyol reduction method over large area substrates while at the same time it provides guidelines for further p-type oxide material and device improvements. [ABSTRACT FROM AUTHOR]

High‐k alkaline lithium oxide (LiOx) thin films are fabricated by spin‐coating method. The LiOx thin films are annealed at different temperatures and characterized by various techniques. An optimized LiOx dielectric is achieved at an annealing temperature of 300 °C and exhibits wide bandgap of ≈5.5 eV, smooth surface, relatively permittivity of ≈6.7, and low leakage current density. The as‐fabricated LiOx thin films are integrated, as gate dielectrics, in both n‐channel indium oxide (In2O3) and p‐channel cupric oxide (CuO) transistors. The optimized In2O3/LiOx thin‐film transistor (TFT) exhibits high performance and high stability, such as Ion/Ioff of 107, electron mobility of 5.69 cm2 V−1 s−1, subthreshold swing of 70 mV dec−1, negligible hysteresis, and threshold voltage shift of 0.1 V under bias stress for 1.5 h. Meanwhile, the p‐channel CuO TFT based on LiOx dielectric shows high Ion/Ioff of 105 and hole mobility of 1.72 cm2 V−1 s−1. All the electrical performances are achieved at an ultra‐low operating voltage of 2 V. Considering the simple procedure, the moderate annealing temperature, and the low power consumption merits, these outstanding characteristics represent a significant advance toward the development of battery compatible and portable electronics. [ABSTRACT FROM AUTHOR]

Solution-processed p-type oxide semiconductors have recently attracted increasing interests for the applications in low-cost optoelectronic devices and low-power consumption complementary metaloxide-semiconductor circuits. In this work, p-type nickel oxide (NiOx) thin films were prepared using low-temperature solution process and integrated as the channel layer in thin-film transistors (TFTs). The electrical properties of NiOx TFTs, together with the characteristics of NiOx thin films, were systematically investigated as a function of annealing temperature. By introducing aqueous high-k aluminum oxide (Al2O3) gate dielectric, the electrical performance of NiOx TFT was improved significantly compared with those based on SiO2 dielectric. Particularly, the hole mobility was found to be 60 times enhancement, quantitatively from 0.07 to 4.4 cm²/V s, which is mainly beneficial from the high areal capacitance of the Al2O3 dielectric and high-quality NiOx/Al2O3 interface. This simple solution-based method for producing p-type oxide TFTs is promising for next-generation oxide-based electronic applications. [ABSTRACT FROM AUTHOR]

In this study, amorphous indium-tungsten oxide (IWO) semiconductor thin films were prepared by an eco-friendly spin-coating process using ethanol and water as solvents. The electrical properties of IWO thin-film transistors (TFTs), together with the structural and morphological characteristics of IWO thin films, were systematically investigated as functions of tungsten concentration and annealing temperature. The optimized IWO channel layer was then integrated on an aqueous aluminum oxide (AlOx) gate dielectric. It is observed that the solution-processed IWO/AlOx TFT presents high stability and improved characteristics, such as an on/off current ratio of 5 × 107, a field-effect mobility of 15.3 cm2 V−1 s−1, a small subthreshold slope of 68 mV dec−1, and a threshold voltage shift of 0.15 V under bias stress for 2 h. The IWO/AlOx TFT could be operated at a low voltage of 2 V, which was 15 times lower than that of conventional SiO2-based devices. The solution-processed IWO thin films synthesized in a green route would be promising candidates for large-area and high-performance low-cost devices. [ABSTRACT FROM AUTHOR]

Solution-processed metal-oxide thin films based on high dielectric constant (k) materials have been extensively studied for use in low-cost and high-performance thin-film transistors (TFTs). Here, scandium oxide (ScOx) is fabricated as a TFT dielectric with excellent electrical properties using a novel water-inducement method. The thin films are annealed at various temperatures and characterized by using X-ray diffraction, atomic-force microscopy, X-ray photoelectron spectroscopy, optical spectroscopy, and a series of electrical measurements. The optimized ScOxthin film exhibits a low-leakage current density of 0.2 nA cm−2 at 2 MV cm−1, a large areal capacitance of 460 nF cm−2 at 20 Hz and a permittivity of 12.1. To verify the possible applications of ScOx thin films as the gate dielectric in complementary metal oxide semiconductor (CMOS) electronics, they were integrated in both n-type InZnO (IZO) and p-type CuO TFTs for testing. The water-induced full oxide IZO/ScOx TFTs exhibit an excellent performance, including a high electron mobility of 27.7 cm2 V−1 s−1, a large current ratio (IonIoff) of 2.7 × 107 and high stability. Moreover, as far as we know it is the first time that solution-processed p-type oxide TFTs based on a high-k dielectric are achieved. The as-fabricated p-type CuO/ScOx TFTs exhibit a large IonIoff of around 105 and a hole mobility of 0.8 cm2 V−1 at an operating voltage of 3 V. To the best of our knowledge, these electrical parameters are among the highest performances for solution-processed p-type TFTs, which represents a great step towards the achievement of low-cost, all-oxide, and low-power consumption CMOS logics. [ABSTRACT FROM AUTHOR]

Copper oxide (CuxO) thin films were fabricated on SiO2/Si substrates by using a solution process. The coated CuxO gel films were treated using a vacuum annealing method at various temperatures (400–700 °C). X-ray diffraction results indicated that the vacuum annealing technique was effective in transforming CuO into Cu2O. Atomic force microscopy images showed that the mean grain size and the surface roughness of the resulting films increased with increasing annealing temperature. To verify the possibility of CuxO thin films as channel layers, the bottom gate structured thin film transistors (TFTs) were integrated. The electrical properties of the as-fabricated CuxO TFTs were improved with increasing processing temperature from 400 to 600 °C. The 600 °C-annealed CuxO TFT exhibited the best electrical performances, including a low threshold voltage of −3.2 V, a large field-effect mobility of 0.29 cm2 V−1 s−1, a small subthreshold swing of 0.8 V dec−1, and an on/off current ratio of 1.6 × 104, respectively. However, with increasing annealing temperature, the electrical properties of the CuxO TFTs were degraded dramatically. These results suggest that solution-processed CuxO TFTs achieved by using a one-step vacuum annealing technique could potentially be used for high-performance p-type electronic devices, which represents a great step towards the further development of low-cost and all-oxide CMOS electronics. [ABSTRACT FROM AUTHOR]

Here, a simple, nontoxic, and inexpensive 'water-inducement' technique for the fabrication of oxide thin films at low annealing temperatures is reported. For water-induced (WI) precursor solution, the solvent is composed of water without additional organic additives and catalysts. The thermogravimetric analysis indicates that the annealing temperature can be lowered by prolonging the annealing time. A systematic study is carried out to reveal the annealing condition dependence on the performance of the thin-film transistors (TFTs). The WI indium-zinc oxide (IZO) TFT integrated on SiO2 dielectric, annealed at 300 °C for 2 h, exhibits a saturation mobility of 3.35 cm2 V−1 s−1 and an on-to-off current ratio of ≈108. Interestingly, through prolonging the annealing time to 4 h, the electrical parameters of IZO TFTs annealed at 230 °C are comparable with the TFTs annealed at 300 °C. Finally, fully WI IZO TFT based on YO x dielectric is integrated and investigated. This TFT device can be regarded as 'green electronics' in a true sense, because no organic-related additives are used during the whole device fabrication process. The as-fabricated IZO/YO x TFT exhibits excellent electron transport characteristics with low operating voltage (≈1.5 V), small subthreshold swing voltage of 65 mV dec−1 and the mobility in excess of 25 cm2 V−1 s−1. [ABSTRACT FROM AUTHOR]