1. Diagnosis of Parkinson's Disease Using Convolutional Neural Network-Based Audio Signal Processing on FPGA.
- Author
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Majidinia, Hamid, Khatib, Farzan, Seyyed Mahdavi Chabok, Seyyed Javad, Kobravi, Hamid Reza, and Rezaeitalab, Fariborz
- Subjects
PARKINSON'S disease ,CONVOLUTIONAL neural networks ,SIGNAL processing ,DEEP learning ,MACHINE learning - Abstract
This study proposes a new method for diagnosing Parkinson's disease using audio signals and FPGA-based convolutional neural networks. The proposed method involves training a convolutional neural network and using deep learning techniques to increase its accuracy. The method is implemented on an FPGA chip to reduce latency and storage space. This work achieves higher accuracy and lower delay than other methods. The study also explores the potential of using the dropout approach during network training to improve the learning of convolutional neural networks. The findings of this study suggest that the proposed method can be a useful tool for diagnosing Parkinson's disease with audio data. Contributions and novelties of this work include the use of FPGA-based convolutional neural networks for Parkinson's disease diagnosis, the implementation of the method on an FPGA chip, and the exploration of the dropout approach for improving the accuracy of convolutional neural networks. The proposed method achieves higher accuracy and lower delay than other methods, making it a useful tool for diagnosing Parkinson's disease with audio data. The use of a new accelerator with a dropout technique and lowering the learning rate to increase detection accuracy is also a novel contribution to the field of machine learning. In addition, the proposed method eliminates the need to store convolution mapping, reducing the chip volume and computational volume, and the integrated chip is much smaller in volume and uses less power than prior generations. The method is developed and trained on audio data to detect Parkinson's disease and then implemented on an FPGA using a high-end hardware accelerator architecture. By reducing the bit width, this method decreases the space used by the logical cells and minimizes latency via the proposed computational model and parallel computations. [ABSTRACT FROM AUTHOR]
- Published
- 2024
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