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This paper presents a methodology for the physical analysis of defects on p-GaN power HEMTs that have been electrically stressed under DC surge or voltage switching stresses. The methodology includes a backside approach for sample preparation and defect localization. It is crucial to adapt the preparation process according to the position of the defect in the device structure (including metallurgy, dielectric layers, epitaxy, etc.), which depends on the type of stress applied. In our study of the reliability of the transistor under increased electrical stress in lifetime operation mode, failure analysis is used to identify the weakest areas in the design with respect to the type of stress applied. This paper presents a failure analysis consisting of techniques such as electrical characterization, photon emission microscopy and lock-in thermography for defect localization, focused ion beam slice and view, transmission electron microscopy analysis, and frontside conductive atomic force microscopy after immersion in hydrofluoric acid. [ABSTRACT FROM AUTHOR]

This study details a three-level hybrid fault-tolerant converter. The definition of an original decoupling solution between the fourth flying capacitor (FC) leg and the three neutral point (NP) clamped-based phases overcomes topology hybridisation issues. Under normal conditions, a control strategy of the FC-based leg leads to a converter NP voltage balance, and decreases the DC side capacitors' volume and cost. Under fault conditions, the presented fault isolation and converter reconfiguration strategies generate a post-fault converter, which is able to operate safely with the added FC-based leg. The proposed topology is an interesting trade-off between converter fault-tolerant capability and its complexity and offers the ability to be simply reconfigured and controlled in the case of switch fault occurrence. Two operation modes under fault conditions are presented and their performances are shown and discussed through simulation results and first experimental tests. [ABSTRACT FROM AUTHOR]

The supervision of semiconductor power devices in operation demonstrates an obvious interest to improve the operating safety of electronic power converters used in critical applications. Unfortunately, this is a significant challenge due to the variability of stress conditions on the one hand and to the difficulty to implement accurate measurement systems in power stages on the other. Using VCE measurement as a real-time supervision method is evaluated here by using aging test results obtained on insulated gate bipolar transistor (IGBT) modules stressed by power cycling. These results are related to the aging of bond wires and metallization, on the top part of the module. Results were obtained in original test benches whose characteristics are overviewed briefly in the first part of this paper, along with a description of test conditions. The second part presents selected results extracted from a larger work and focusing on the VCE evolution with respect to degradations of the module's top part. Their analysis highlights the potential of VCE measurement. The last part proposes the principle of a specific system able to achieve real-time VCE supervision in the test benches in operation. [ABSTRACT FROM PUBLISHER]

This paper presents an experimental study on the ageing of insulated-gate bipolar transistor (IGBT) power modules. The aim is to identify the effects of power cycling on these devices with high baseplate temperatures (60 ^\circ\C to 90 ^ \circ\C) and wide temperature swings (60 ^\circ \C to 100 ^\circ\C). These values for thermal stresses have been defined according to automotive applications. The test conditions are provided by two types of test benches that will be described in this paper. The changes in electrical and thermal indicators are observed regularly by a monitoring system. At the end of the test (reaching damage criterion or failure), different analyses are performed (acoustic scanning and SEM imaging), and the damage is listed systematically. Nineteen samples of 600-V 200-A IGBT modules were thus aged using five different power-cycling protocols. The final summary of results shows that ageing mechanisms mainly concern wire bonds and emitter metallization, with gradual impact depending on protocol severity. [ABSTRACT FROM AUTHOR]

In this paper, a new three-level (3L) converter is presented. It is called 3L Vienna neutral-point-clamped (3L-VNPC) converter and consists of two stacked high-frequency (HF) commutation cells working with a shared power device. The HF cells are connected to a single-phase switched bridge controlled at low frequency. The 3L-VNPC topology is extended to 3L active VNPC (3L-AVNPC) concept, which is generalized for five levels (5L) and N odd voltage levels (N \L). The proposed multilevel converters can be seen as two cascaded voltage stages. The high-voltage stage is specific to the single-phase switched bridge, while the low-voltage (LV) stage corresponds to the stacked HF cells with shared power devices. The new concept AVNPC is a useful and suitable solution for medium-voltage applications, where small modulation index (M) is as crucial as large M. The analyses of the new converters are verified by simulations both for 3L and for 5L topologies, and their features are generalized for N\L. Experimental results for single-phase 3L-AVNPC converter on an LV test bench are also provided to validate the proper operation of the new concept. [ABSTRACT FROM AUTHOR]

This paper is related to faults that can appear in multilevel (ML) inverters, which have a high number of components. This is a subject of increasing importance in high-power inverters. First, methods to identify a fault are classified and briefly described for each topology. In addition, a number of strategies and hardware modifications that allow for operation in faulty conditions are also presented. As a result of the analyzed works, it can be concluded that ML inverters can significantly increase their availability and are able to operate even with some faulty components. [ABSTRACT FROM AUTHOR]

This paper presents an original concept in which integrated over-voltage and/or over-current protections of power devices are used to produce a self-switching operation. Such a commutation is shown as a possible combination with conventional forced-switching and spontaneous-switching to simplify direct regenerative ac-dc conversion, insulating dc-ac-dc conversion and finally direct ac-ac conversion. Experimental results prove the feasibility of the concept through which the self turn-off operation is likely to offer the best practical gains. [ABSTRACT FROM AUTHOR]

The power characteristics of wind turbines are non- linear. It is particularly true for vertical-axis turbines whose provided power is very sensitive to the load. Thus, controlling the operating point is essential to optimize the energetic behavior. Several control strategies (maximum power point tracking) can be used for the energy conversion. If the wind-turbine characteristic Cp (λ) is supposed to be a priori known, it can be used for optimal control of the torque, speed, or system output power. On the contrary, if this characteristic is unknown, an operational seeking algorithm such as fuzzy logic has to be implemented. Several structures with different associated complexity degrees can be used, in particular, the structure of the ac-dc conversion, which can be either a pulsewidth-modulation voltage-source rectifier or a simple diode bridge. A comparative study of the corresponding control strategies and architectures is proposed in this paper regarding the tradeoffs between structure complexity and energy efficiency. The analysis is based on simulations and experiments. [ABSTRACT FROM AUTHOR]

The test and the characterization of medium or high-power electronic converters, under nominal operating conditions, are made difficult by the requirement of high-power electrical source and load. In addition, the energy lost during the test may be very significant. The opposition method, which consists of an association of two identical converters supplied by the same source, one operating as a generator, the other as a receptor, can be a better way to do these test. Another advantage is the possibility to realize accurate measurements of the different losses in the converters under test. In the first part of this paper, the characteristics of the method concerning loss measurements are compared to those of the electrical or calorimetric methods, then it is shown how it can be applied to different types of power electronic converters, choppers, switched mode power supplies, and pulsewidth modulation inverters. In the second part, different examples of studies conducted by the authors, and using this method, are presented. They have varying goals, from the test of soft-switching inverters to the characterization of integrated gate-commutated thyristor (IGCT) devices mounted into 2-MW choppers. [ABSTRACT FROM AUTHOR]

Examines the consequences of faults in hard-switching and soft-switching multicell converters. Use of different arrangement of components; Differences of consequence of faults; Description of solutions to minimize the consequences of major faults.

Analyzes the properties of multicell converters. Analysis of the different ways to introduce soft switching in multicell converters; Concept of distributing power over several switches; Description of direct ac-ac converters using the multicell approach.

This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON. [ABSTRACT FROM AUTHOR]