23 results on '"Pamunuwa D"'
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2. 3-D integration and the limits of silicon computation.
3. Optimal signaling techniques for Through Silicon Vias in 3-D integrated circuit packages.
4. On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits.
5. Scalability of network-on-chip communication architecture for 3-D meshes.
6. Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits.
7. Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.
8. Design of robust molecular electronic circuits.
9. Molecular electronics device modeling for system design.
10. Delay-Balanced Smart Repeaters for On-Chip Global Signaling.
11. Nanodevices: from novelty toys to functional devices - an integration perspective.
12. Crosstalk immune interconnect driver design.
13. Analytic modeling of interconnects for deep sub-micron circuits.
14. On dynamic delay and repeater insertion in distributed capacitively coupled interconnects.
15. Repeater insertion to minimise delay in coupled interconnects.
16. Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.
17. Modeling noise and delay in VLSI circuits.
18. Memory Technology for Extended Large-Scale Integration in Future Electronics Applications.
19. A global wire planning scheme for Network-on-Chip.
20. Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees.
21. Optimising bandwidth over deep sub-micron interconnect.
22. On dynamic delay and repeater insertion.
23. Combating digital noise in high speed ULSI circuits using binary BCH encoding.
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