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In the era of high component density chips, power consumption has emerged as a forefront design metric. Both power and performance of a system are significantly influenced by the voltage controlled oscillator (VCO) in many analog and digital applications. Lowering the supply voltage is the most effective technique to reduce the power consumption. This paper therefore investigates the challenges in designing the CSVCO at lower voltages. Performance and power consumption of a five stage current starved VCO (CSVCO) is investigated over a wide range of supply voltages. Along with increasing power density, variability poses a significant challenge at lower technology nodes. The analysis of impact of threshold voltage, length, supply voltage, and temperature variation on 3s/µ (%) delay variability of CSVCO output pulse at different supply voltages ranging from maximum (nominal) voltage in the 32 nm technology (0.9V) to (0.3V) is done independently as well as comprehensively using Monte Carlo SPICE simulations. A non-linear variation of delay variability is observed with various sources of variation over a wide supply voltage range. The results reveal that the process and voltage variations have significant impact on delay variability of CSVCO compared to the temperature variations. It is observed from the simulation results that at the supply voltage (Vdd) of 0.4V, power consumption reduces by 257 times at the cost of increased 3s/µ delay variability by 8.17% compared to the power consumption and variability at nominal Vdd of 0.9V.The variability is further exacerbated at Vdd=0.3V as seen from the simulation results. [ABSTRACT FROM AUTHOR]

In current bulk CMOS technology, semiconductor devices are continuously scaled down to achieve higher speed and packing density. This continuous scaling of MOSFET below 45nm technology node gives rise to short channel effects like DIBL, Vt roll off, random dopant fluctuations, mobility degradation etc. There is a need to explore devices beyond bulk CMOS that exhibits higher ION/IOFF ratio, scalability, better channel electrostatics and robustness against process variations. Tunnel Field Effect Transistor (TFET) is considered as one of the most promising device to provide scaling benefits with significant reduction in short channel effects. This paper presents a comparative study of CMOS and TFET based Second Generation Current conveyor (CCII) at a supply voltage of ±0.3V and bias current of 1nA at 32nm technology node. The performance parameters of CCII have been investigated in terms of current gain (α), voltage gain (β), current and voltage bandwidths, resistances and their respective bandwidths at various ports of CCII. It has been found that there is considerable improvement in most of the above parameters using TFET. [ABSTRACT FROM AUTHOR]

Aggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selecting Vth and TOX is much more flexible for subthreshold circuits at low voltage level than superthreshold circuits. In order to obtain better performance from a device under subthreshold conditions, it is necessary to investigate and optimize the process and geometry parameters of a Si MOSFET at nanometer technology node. This paper calibrates the fabrication process parameters and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length. Thereafter, the calibrated device for superthreshold application is optimized for better performance under subthreshold conditions using TCAD simulation. The device simulated in this work shows 9.89% improvement in subthreshold slope and 34% advantage in ION/IOFF ratio for the same drive current. [ABSTRACT FROM AUTHOR]

Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most promising upcoming devices like CNFET and DG FinFET in subthreshold regions. Effect of PVT variation on performance of CNFET and DG FinFET has been explored and it is found that CNFET is more robust than DG-FinFET under subthreshold conditions against PVT variations. [ABSTRACT FROM AUTHOR]