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This paper studies ON/OFF control of a dc-dc system that contains multiple active-clamp LLC resonant modules operating in parallel. The architecture and the ON/OFF control method yield high overall efficiency and fast transient responses. Two converter models are introduced: 1) a high-frequency model to determine a gate timing sequence that enables fast ON/OFF control, and 2) an averaged model to assist in the system control loop design. The models and the ON/OFF control method are verified by experiments on a prototype consisting of two 1-MHz, 24-3.3-V, 5-W active-clamp LLC modules. The performance of PI and PID system controllers is compared, and capacitor size is analyzed by simulations on systems containing up to 20 modules. [ABSTRACT FROM AUTHOR]

This paper presents an alternative modulation approach for digitally controlled dc–dc switching converters, which exploits the natural jittering activity of a digital hysteretic feedback loop in order to provide an effective increase in resolution. The proposed structure replaces conventional high-resolution digital pulsewidth modulators (DPWMs) or sigma–delta-based (ΣΔ-DPWM) solutions with a single, fully digital block featuring reduced complexity, high resolution, improved noise performance, and small-signal characteristics, enabling the design of accurate, high-bandwidth digital feedback loops with minimum hardware resources. A stochastic modeling approach is developed for the proposed structure, which allows the derivation of a simple and effective switching frequency-control criterion. Analysis, simulation, and experimental tests are shown to validate the properties of the proposed digital hysteretic modulator. [ABSTRACT FROM AUTHOR]

This paper introduces a single-phase digital power-factor correction (PFC) control approach that requires no input voltage sensing or explicit current-loop compensation, yet results in low-harmonic operation over a universal input voltage range and loads ranging from high-power operation in continuous conduction mode down to the near-zero load. The controller is based on low-resolution A/D converters and digital pulsewidth modulator, requires no microcontroller or DSP programming, and is well suited for a simple, low-cost integrated-circuit realization, or as a hardware description language core suitable for integration with other power control and power management functions. Experimental verification results are shown for a 300-W boost PFC rectifier. [ABSTRACT FROM PUBLISHER]

This paper addresses the problem of time-optimal load-transient response in digitally controlled dc–dc buck converters incorporating an inductor current limitation. The concept of current-limited, time-optimal control (CL-TOC) is introduced and compared to the conventional unconstrained time-optimal solution. A fundamental tradeoff between maximum-allowed current overshoot and voltage recovery time is recognized and analytically formulated, thus providing the engineer with the necessary analytical tools for performance evaluation. Furthermore, the minimum number of switching actions required to handle a generic CL-TOC transient is determined, thus leading to the formulation of a minimum-switch CL-TOC concept. Two distinct approaches for implementing minimum-switch digital CL-TOC are then introduced. The first method extends a parameter-independent time-optimal control that has the advantage of achieving the time-optimal switching sequence without the need for a prior knowledge of the output filter LC parameters or input voltage. The second approach implements a near CL-TOC employing the switching-surface concept and defining the current limitation in the state space. Experimental results are provided to validate the theory and demonstrate the effectiveness of the approaches. [ABSTRACT FROM PUBLISHER]

This paper focuses on efficiency improvements and harmonic distortion reductions in digitally controlled single-phase boost power-factor-correction (PFC) rectifiers operating over wide load range. Based on a discontinuous conduction mode (DCM) detection circuit, a predictive current control law is modified to improve current shaping in both DCM and continuous conduction mode (CCM). Adaptive switching and adaptive frequency control techniques are introduced to reduce switching losses and improve efficiency at light loads. Experimental results are shown for a 300 W boost PFC rectifier. [ABSTRACT FROM PUBLISHER]

This letter presents an online adaptive tuning technique for digitally controlled switched-mode power supplies (SMPS). The approach is based on continuous monitoring of the system crossover frequency and phase margin, followed by a multi-input-multi-output (MI \40) control loop that continuously and concurrently tunes the compensator parameters to meet crossover frequency and phase margin targets. Continuous stability margin monitoring is achieved by injecting a small digital square-wave signal between the digital compensator and the digital pulsewidth modulator. The MIMO loop adaptively adjusts the compensator parameters to minimize the error between the desired and measured crossover frequency and phase margin. Small-signal models are derived, and the MEMO control loop is designed to achieve stability and performance over a wide range of operating conditions. Using modest hardware resources, the proposed approach enables adaptive tuning during normal SMPS operation. Experimental results demonstrating system functionality are presented for a synchronous buck SMPS. [ABSTRACT FROM AUTHOR]

This paper introduces an approach to achieve optimum dead times in dc-dc converters with synchronous rectifiers without sensing any of the power-stage signals other than the output voltage. The dead times are adjusted adaptively to minimize the duty-cycle command, which results in maximization of the converter efficiency. The method is particularly well suited for digital controller implementation, requiring no additional analog components or modifications of standard gate-drive circuitry. Experimental results for a digitally controlled 5 V-to-1 V, 5-A synchronous buck converter demonstrate practical implementation of the sensorless dead-time optimization algorithm. [ABSTRACT FROM AUTHOR]

This letter proposes a three-level buck converter for tracking applications such as envelope-tracking in radio frequency power amplifiers (RFPAs). It is shown that the three-level buck converter can offer advantages in terms of switching ripples, losses, bandwidth, or the size of magnetic components compared to a standard buck or a two-phase buck converter. Experimental results illustrate improved efficiency and ripple rejection in an RFPA envelope-tracking application representative for low-power battery-operated systems. [ABSTRACT FROM AUTHOR]

In converters for power-factor-correction (PFC), the universal-input capability, i.e., the ability to operate from any ac line voltage world-wide, comes with a heavy penalty in terms of component stresses and losses, and with restrictions on the dc output voltage. In this paper, we propose a new two-switch topology, boost-interleaved buck-boost (BoIBB) converter, which can offer significant performance improvements over single-switch buck-boost converters (including flyback, SEPIC, or Cuk topologies) or other two-switch buck-boost converters in universal-input PFC applications. The paper presents an analysis of the converter operation and component stresses, as well as design guidelines. High efficiency (over 93%) throughout the universal-input ac line voltage range is demonstrated on an experimental 100-W, 200-V dc output, universal-input BOIBB PFC rectifier. [ABSTRACT FROM AUTHOR]

This paper describes design and implementation of a digitally controlled dc/dc converter that provides a dynamically adjustable supply voltage for a radio frequency power amplifier (RFPA). The techniques employed in the design include a combination of constant-frequency continuous conduction mode (CCM) and a variable-frequency discontinuous conduction mode to achieve very high converter efficiency over a wide range of output power levels. The variable-frequency converter control is accomplished using a current-estimator circuit, which eliminates the need for current sensing. A field-programmable gate array (FPGA)-based digital controller implementation allows programmability of the mode transition and other controller parameters. In the complete experimental system, which consists of the digitally controlled dc/dc converter and a class-E RFPA operating at 10 GHz, experimental results show that the overall system efficiency is significantly improved over a wide range of RFPA output power levels. [ABSTRACT FROM AUTHOR]

Multifunctional RF front ends need to transmit different types of signals while maintaining efficiency and signal quality. This paper addresses efficient transmitter power amplifiers (PAs) for signals with varying peak-to-average ratios, requiring simultaneous efficiency and linearity. Linearity characterization of class-E high-efficiency PAs operating in envelope elimination and restoration (EER) mode is discussed. Specifically, a 67 % -efficient 10-GHz MESFET PA is characterized in terms of its AM-AM, AM-PM conversion and intermodulation products. Measurements of intermodulation distortion are compared with harmonic-balance simulations using TriQuint's Own Model provided by the device manufacturer. It is shown experimentally and through simulations that the amplifier in the EER mode has improved linearity while maintaining high-efficiency operation. [ABSTRACT FROM AUTHOR]

This paper describes the design, implementation, and characterization of a high-efficiency 10-GHz amplifier with dynamic drain bias control that maintains high efficiency over a range of output power levels. The power amplifier (PA) operates in class-E switched mode with 67% drain efficiency at an output power of 20.3 dBm, 0.7 dB less than the specified maximum power for the device. A coupler and detector at the output of the PA provide a feedback signal to the drain-bias controller based on a 96% efficient Buck dc-dc converter. When compared with a PA with constant drain bias (4 V), the average efficiency of the PA with dynamic biasing is improved by a factor of 1.4. Over an output power between 15-20 dBm, the drain bias varies from 2 to 4 V, and the efficiency improves from 22% to 65% at the lower power level. The efficiency includes the losses in the dc-dc converter. [ABSTRACT FROM AUTHOR]

In the presence of partial shading and other mismatch factors, bypass diodes may not offer complete elimination of excessive power dissipation due to cell reverse biasing, commonly referred to as hot-spotting in photovoltaic (PV) systems. As a result, PV systems may experience higher failure rates and accelerated ageing. In this paper, a cell-level simulation model is used to assess occurrence of hot-spotting events in a representative residential rooftop system scenario featuring a moderate shading environment. The approach is further used to examine how well distributed power electronics converters mitigate the effects of partial shading and other sources of mismatch by preventing activation of bypass diodes and thereby reducing the chances of heavy power dissipation and hot-spotting in mismatched cells. The simulation results confirm that the occurrence of heavy power dissipation is reduced in all distributed power electronics architectures, and that submodule-level converters offer nearly 100% mitigation of hot-spotting. In addition, the paper further elaborates on the possibility of hot-spot-induced permanent damage, predicting a lifetime energy loss above 15%. This energy loss is fully recoverable with submodule-level power converters that mitigate hot-spotting and prevent the damage. [ABSTRACT FROM AUTHOR]