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Oscillations in the granule cell layer (GCL) of the cerebellar cortex have been related to behavior and could facilitate communication with the cerebral cortex. These local field potential (LFP) oscillations, strong at 4–12 Hz in the rodent cerebellar cortex during awake immobility, should also be an indicator of an underlying influence on the patterns of the cerebellar cortex neuronal firing during rest. To address this hypothesis, cerebellar cortex LFPs and simultaneous single-neuron activity were collected during LFP oscillatory periods in the GCL of awake resting rats. During these oscillatory episodes, different types of units across the GCL and Purkinje cell layers showed variable phase-relation with the oscillatory cycles. Overall, 74% of the Golgi cell firing and 54% of the Purkinje cell simple spike (SS) firing were phase-locked with the oscillations, displaying a clear phase relationship. Despite this tendency, fewer Golgi cells (50%) and Purkinje cell's SSs (25%) showed an oscillatory firing pattern. Oscillatory phase-locked spikes for the Golgi and Purkinje cells occurred towards the peak of the LFP cycle. GCL LFP oscillations had a strong capacity to predict the timing of Golgi cell spiking activity, indicating a strong influence of this oscillatory phenomenon over the GCL. Phase-locking was not as prominent for the Purkinje cell SS firing, indicating a weaker influence over the Purkinje cell layer, yet a similar phase relation. Overall, synaptic activity underlying GCL LFP oscillations likely exert an influence on neuronal population firing patterns in the cerebellar cortex in the awake resting state and could have a preparatory neural network shaping capacity serving as a neural baseline for upcoming cerebellar operations. [ABSTRACT FROM AUTHOR]

Convolutional Neural Networks (CNNs) and Deep Neural Networks (DNNs) have gained significant popularity in several classification and regression applications. The massive computation and memory requirements of DNN and CNN architectures pose particular challenges for their FPGA implementation. Moreover, programming FPGAs requires hardware-specific knowledge that many machine-learning researchers do not possess. To make the power and versatility of FPGAs available to a wider deep learning user community and to improve DNN design efficiency, we introduce POLYBiNN, an efficient FPGA-based inference engine for DNNs and CNNs. POLYBiNN is composed of a stack of decision trees, which are binary classifiers in nature, and it utilizes AND-OR gates instead of multipliers and accumulators. POLYBiNN is a memory-free inference engine that drastically cuts hardware costs. We also propose a tool for the automatic generation of a low-level hardware description of the trained POLYBiNN for a given application. We evaluate POLYBiNN and the tool for several datasets that are normally solved using fully connected layers. On the MNIST dataset, when implemented in a ZYNQ-7000 ZC706 FPGA, the system achieves a throughput of up to 100 million image classifications per second with 90 ns latency and 97.26% accuracy. Moreover, POLYBiNN consumes 8× less power than the best previously published implementations, and it does not require any memory access. We also show how POLYBiNN can be used instead of the fully connected layers of a CNN and apply this approach to the CIFAR-10 dataset. [ABSTRACT FROM AUTHOR]

Due to the emergence of new network applications, current IP lookup engines must support high bandwidth, low lookup latency, and the ongoing growth of IPv6 networks. However, the existing solutions are not designed to address jointly these three requirements. This paper introduces SHIP, an IPv6 lookup algorithm that exploits prefix characteristics to build a data structure designed to meet future application requirements. Based on the prefix length distribution and prefix density, prefixes are first clustered into groups sharing similar characteristics and then encoded in hybrid trie-trees. The resulting memory-efficient and scalable data structure can be stored in low-latency memories and allows the traversal process to be parallelized and pipelined in order to support high packet bandwidth in hardware. In addition, SHIP supports incremental updates. Evaluated on real and synthetic IPv6 prefix tables, SHIP has a logarithmic scaling factor in terms of the number of memory accesses and a linear memory consumption scaling. Compared with other well-known approaches, SHIP reduces the required amount of memory per prefix by 87%. When implemented on a state-of-the-art field-programmable gate array (FPGA), the proposed architecture can support processing 588 million packets per second. [ABSTRACT FROM AUTHOR]

Blood vessel segmentation from high-resolution fundus images is a necessary step in several retinal pathologies detection. Automatic blood vessel segmentation is a computing-intensive task, which raises the need for acceleration with hardware architectures. In this paper, we propose two architectures for blood vessel segmentation using a matched filter (MF). The first architecture is a scalable hardware architecture, while the second one is an application-specific instruction-set processor. An efficient, real-time hardware implementation of the algorithm is made possible through parallel processing and efficient resource sharing. A tool for the automatic generation of particularized HDL descriptions of the architecture is proposed. The tool starts from a common architecture template and takes as input the parameters of the MF. A designer thus gains a significant amount of flexibility and productivity with the parameter selection problem and the evaluation of corresponding implementations. Several designs were verified and implemented on an FPGA platform. Performance in terms of area utilization and maximum frequency are reported. The results show significant improvement over state-of-the-art implementations, by up to a factor of 14× for high-resolution fundus images. The second architecture is based on the Tensilica Xtensa LX processor. With only two additional custom instructions requiring an additional 4× the area of the basic processor, the ASIP achieves a significant speedup of 7.76× when compared to the basic processor, while retaining all its flexibility. [ABSTRACT FROM AUTHOR]

In this paper, we present a simple yet effective image deblurring method to produce ringing-free deblurred images. Our work is inspired by the observation that large-scale deblurring ringing artifacts are measurable through a multi-resolution pyramid of low-pass filtering of the blurred-deblurred image pair. We propose to model such a quantification as a convex cost function and minimize it directly in the deblurring process in order to reduce ringing regardless of its cause. An efficient primal-dual algorithm is proposed as a solution to this optimization problem. Since the regularization is more biased toward ringing patterns, the details of the reconstructed image are prevented from over-smoothing. An inevitable source of ringing is sensor saturation which can be detected costlessly contrary to most other sources of ringing. However, dealing with the saturation effect in deblurring introduces a non-linear operator in optimization problem. In this paper, we also introduce a linear approximation as a solution to handling saturation in the proposed deblurring method. As a result of these steps, we significantly enhance the quality of the deblurred images. Experimental results and quantitative evaluations demonstrate that the proposed method performs favorably against state-of-the-art image deblurring methods. [ABSTRACT FROM AUTHOR]

In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduction. These reduced partial products are added in optimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction. Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers. Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results. [ABSTRACT FROM AUTHOR]

The development of an automatic telemedicine system for computer-aided screening and grading of diabetic retinopathy depends on reliable detection of retinal lesions in fundus images. In this paper, a novel method for automatic detection of both microaneurysms and hemorrhages in color fundus images is described and validated. The main contribution is a new set of shape features, called Dynamic Shape Features, that do not require precise segmentation of the regions to be classified. These features represent the evolution of the shape during image flooding and allow to discriminate between lesions and vessel segments. The method is validated per-lesion and per-image using six databases, four of which are publicly available. It proves to be robust with respect to variability in image resolution, quality and acquisition system. On the Retinopathy Online Challenge's database, the method achieves a FROC score of 0.420 which ranks it fourth. On the Messidor database, when detecting images with diabetic retinopathy, the proposed method achieves an area under the ROC curve of 0.899, comparable to the score of human experts, and it outperforms state-of-the-art approaches. [ABSTRACT FROM AUTHOR]

Bit-width allocation has a crucial impact on hardware efficiency and accuracy of fixed-point arithmetic circuits. This paper introduces a new accuracy-guaranteed word-length optimization approach for feed-forward fixed-point designs. This method uses affine arithmetic, which is a well-known analytical technique, for both range and precision analyses. This paper introduces an acceleration technique and two new semianalytical algorithms for precision analysis. While the first algorithm follows a progressive search strategy, the second one uses a tree-shaped search method for fractional width optimization. The algorithms offer two different time-complexity/cost efficiency tradeoffs. The first algorithm has polynomial complexity and achieves comparable results with existing heuristic approaches. The second algorithm has exponential complexity, but it achieves near-optimal results compared to the exhaustive search method. A commonly used set of case studies is used to evaluate the efficiency of the proposed techniques and algorithms in terms of optimization time and hardware cost. The first and second algorithms achieve 10.9% and 13.1% improvements in area, respectively, over uniform fractional width allocation. The proposed acceleration technique reduces the complexity of the fractional width selection problem by an average of 20.3%. [ABSTRACT FROM PUBLISHER]

Computer vision is a noninvasive method for monitoring laboratory animals. In this article, we propose a robust tracking method that is capable of extracting a rodent from a frame under uncontrolled normal laboratory conditions. The method consists of two steps. First, a sliding window combines three features to coarsely track the animal. Then, it uses the edglets of the rodent to adjust the tracked region to the animal's boundary. The method achieves an average tracking error that is smaller than a representative state-of-the-art method. [ABSTRACT FROM PUBLISHER]

This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12\times and 243\times, and energy consumption reduction factors between 13 and 262. [ABSTRACT FROM AUTHOR]

Acousto-electric charge conveyance induced by a surface acoustic wave (SAW) is employed to dissociate photogenerated excitons. Over macroscopic distances, both electrons and holes are injected sequentially into a remotely positioned, isolated and high quality quantum emitter, a self-assembled quantum post. This process is found to be highly efficient and to exhibit improved stability at high acoustic powers when compared to direct optical pumping at the position of the quantum post. These characteristics are attributed to the wide matrix quantum well in which charge conveyance occurs and to the larger number of carriers available for injection in the remote configuration, respectively. The emission of such pumped quantum posts is dominated by recombination of neutral excitons and fully directional when the propagation direction of the SAW and the position of the quantum post are reversed. [ABSTRACT FROM AUTHOR]

This paper presents an embedded implementation approach of land vehicle navigation involving a Multi Sensor System (MSS) consisting of a single-axis gyroscope and an odometer integrated with GPS receiver. With the assumption that the vehicle stays mostly in the horizontal plane, the vehicle speed obtained from the odometer measurements is decomposed into east and north velocities by using heading information from the gyroscope. Subsequently, the vehicle's position in latitude and longitude are determined. MSS errors are estimated by an integrated MSS/GPS Kalman filter (KF) which relies on a dynamic error model of position, velocity and heading as well as stochastic models for gyroscope and odometer errors. In case of a GPS outage, the designed KF module provides positioning information. The decentralized KF algorithm is described in software and is executed on an embedded soft core processor containing a single precision floating point unit. Results were validated imposing numerous simulated GPS outages of varied lengths on road test trajectory data of GPS receiver, car chip odometer and single axis MEMS based gyro. The length of the simulated GPS outages varied from 36 s to 425 s on three different road trajectories. Results show a maximum positional error of 110 m for an outage of 120s duration and a minimum positional error of 14 m for an outage of 60 s duration with respect to the reference trajectory. [ABSTRACT FROM AUTHOR]

Aim: Melatonin (MT) is a neurohormone produced and secreted primarily by the pineal gland in a circadian manner, and mainly acts through 2 receptor subtypes: MT1 and MT2 in humans. The diversity in their tissue distribution is in favor of different functions for each receptor subtype. Selective modulators are therefore required to determine the physiological roles of these melatonin receptor subtypes and their implications in pathological processes. Methods: A homogenous MT1/MT2 receptor binding assay was established for high-throughput screening of new ligands at the hMT1 and/or hMT2 receptors. The functional properties (agonists or antagonists) were assessed by a conventional guanosine-5′[γ-35S] triphosphate (GTP-γS) assay. Results: Three hMT1 receptor-selective small molecule antagonists and 1 hMT2 receptor-selective small molecule antagonist with novel structural features were identified following a high-throughput screening campaign of 48 240 synthetic and natural compounds. Conclusion: The findings may assist in the expansion of chemical probes to these 2 receptor subtypes. [ABSTRACT FROM AUTHOR]

Aim: To find new antagonists on human melanin-concentrating hormone recep-tor-1 (MCHR-1) through high-throughput screening (HTS) of a diverse compound library. Methods: MCHR-1, [3H]SNAP7941, and FlashBlue G-protein-coupled receptor beads were used to measure the receptor-binding activities of various compounds based on scintillation proximity assay (SPA) technology. The guanosine 5′ (γ-[35S]thio) triphosphate ([35S]GTPγS) binding assay was subsequently applied to functionally characterize the “hits” identified by the HTS campaign. Results: Of the 48 240 compounds screened with the SPA method, 12 hits were confirmed to possess MCHR-1 binding activities, 8 were functionally studied subsequently with the [35S]GTPγS binding assay, and only 1 compound (NC127816) displayed moderate human MCHR-1 binding affinity ( Ki=115.7 nmol/L) and relatively potent antagonism ( KB=23.8 nmol/L). This compound shares a novel scaffold (1-ethoxy-2 H-2-aza-1-phospha-naphthalene 1-oxide) with 3 other analogs in the group. Conclusion: Considering the marked difference in molecular shape and electrostatic status between NC127816 and the structures reported elsewhere, we anticipate that its derivatives may represent a new class of potent MCHR-1 modulators. [ABSTRACT FROM AUTHOR]

This paper presents two simple combinational logic design approaches for bit-parallel approximate squarers of unsigned numbers. The design approaches are suitable for squarers of any bit length, and are particularly well suited for implementation in look-up table-based field-programmable gate arrays. It is shown that the hardware requirements grow linearly with the input bit width, as opposed to recent work where the complexity grows quadratically. This is a consequence of the optimized function selection algorithm which limits the number of input variables to each bit function. It is also shown that the critical path delay is independent of the input bit width. The proposed sets of Boolean equations are very simple to use and lend themselves very well to a parameterized HDL description. For a 7-bit input, the maximum relative error (MRE) and average relative error (ARE) are as low as 9.44% and 2.47%, respectively. For very wide input, the best MRE and ARE figures asymptotically approach 11.3% and 4.5%. [ABSTRACT FROM AUTHOR]

This article is based on remarks made at the Sixth International Arbitration Congress by the highest ranking judge of Trance to a working group of judges, arbitrators, law professors, and practitioners, who explored the relationships between arbitration and the courts throughout the world. The article first expresses agreement with a paper presented by the reporter of the working group and then goes on to comment candidly on the views of Trench judges toward arbitration. [ABSTRACT FROM AUTHOR]

This article discusses various issues related to role of yawning in human physiology. Yawning occurs in passive activities when it is necessary to maintain a certain level of vigilance, which is then followed by an acceleration of the electro-encephalographic rhythms. It has a non-verbal communicative status. Yawning is also a symptom in intracranial hypertension, migraine, or side effects of dopaminergic drugs. Contagious yawning is triggered by seeing, hearing, or even thinking about someone else yawning. The phenomenon has been investigated with functional magnetic resonance imaging. However, further studies are needed to explore the various aspects of contagious yawning.