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This paper presents a fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports a programmable regulated power supply ranging from 2.6 to 3.2 V out of a 5 V input supply. The proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance to maximize the load current driving capability while minimizing the bottom-plate capacitance loss. The control circuits use a low power supply provided by a small internal low-drop output (LDO) connected to the internal load voltage (VL_dw) from the 2-to-1_dw, and low swing level-shifted gate-driving signals are generated using the internal load voltage (VL_dw). Therefore, the proposed implementation reduces control circuit and switching power consumptions. The programmable power supply voltage is regulated by means of a pulse frequency modulation (PFM) technique with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) to maintain high efficiency over a wide range of load currents. The proposed on-chip SC DC-DC converter is designed and simulated using high-voltage 0.35 μm bipolar, complementary metal-oxide-semiconductor (CMOS) and DMOS (BCDMOS) technology. It achieves a peak efficiency of 74% when delivering an 8 mA load current at a 3.2 V supply voltage level, and it provides a maximum output power of 48 mW (IL = 15 mA at VL_up = 3.2 V) at 70.5% efficiency. The proposed on-chip SC voltage regulator shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 mW to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage. [ABSTRACT FROM AUTHOR]

In nanometer technology, accurate aging prediction of MOSFET digital circuits is one of the most critical issues for more reliable adaptive system design. This paper proposes a new on-chip aging prediction circuit to monitor BTI and HCI aging effects on digital circuits. The proposed circuit deploys a flip-flop based delay detector for monitoring a guardband violation of sequential logics. The outputs of the proposed circuit can be used as a control signal in reliable self-adaptive systems. A 0.11µm CMOS technology has been used to implement and evaluate the proposed circuits. [ABSTRACT FROM AUTHOR]

This paper presents a jitter decomposition method in the test of serial data channels. It is difficult to detect minor adjacent spectral jitter components due to frequency leakage in the jitter decomposition. Especially, when spectral jitter decomposition in random jitter (RJ) and periodic jitter (PJ) is performed, some degree of the PJ leakage can occur. The PJ leakage can cause serious error in separation PJ and RJ. Therefore, in this paper, a new method to avoid PJ leakage has been proposed. The proposed method shows significant improvement in PJ leakage control. [ABSTRACT FROM AUTHOR]

A novel power gating (PG) structure using only low-threshold-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed to extend the PG to an ultralow-voltage region (∼0.3 V). The proposed structure deploys series-connected Iow-Vth footers with two virtual ground ports and selectively chooses the logic cells for connecting them to each virtual ground port according to the delay criticality. Furthermore, additional circuitry is designed to reduce not only the subthreshold leakage current but also the gate-tunneling leakage and to reduce the wake-up time and rush current compared to the conventional PG. The total PG switch size of the proposed PG structure including the additional circuits is less than the conventional one. The simulation results are compared to those of other well-known circuit schemes and show that, in the ultralow-voltage region, the other high-Vth-based PG schemes cannot be used due to the impractical delay increase and long wake-up time, whereas the proposed PG structure keeps the balance among the critical PG issues. The proposed PG is evaluated using inverter chains and ISCAS85 benchmark circuits at 0.6-V supply voltage, which are designed using 45-nm complementary metal-oxide-semiconductor predictive technology model. [ABSTRACT FROM AUTHOR]

This paper presents a novel statistical characterization for accurate timing and a new probabilistic-based analysis for estimating the leakage power in partially depleted silicon-on-insulator (PD-SOI) circuits in 100-nm BSIMSOI3.2 technology. This paper shows that the accuracy of modeling the leakage current in PD-SOI complementary metal-oxide-semiconductor (CMOS) circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fan-out effect, along with a new input-independent method for estimating the leakage power based on a probabilistic approach. The proposed timing and leakage power estimate algorithms are implemented in MATLAB, HSPICE, and C. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5%, compared with random simulation results. [ABSTRACT FROM AUTHOR]

This paper presents a novel modeling analysis of jitter as applicable to testing of serial data channels. Jitter is analyzed by considering separate and combined components. The primary goal is the generation of a signal containing a known amount of each jitter component. This signal can then be used for testing high speed serial data channels. Initially, jitter components are analyzed and modeled individually. Next, sequences for combining them are modeled, simulated and evaluated. Model simulation using Matlab is utilized to show the unique features of the components when they are combined into different injection sequences for producing the total jitter. Sequence dependency is investigated in depth and the validity of superposition of jitter components for typical values is confirmed. A good agreement between theory and simulation is verified; these results allow test engineers to have an insight into the interactions among jitter components in serial data channels. [ABSTRACT FROM PUBLISHER]