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We present an electron spin resonance (ESR) approach to characterize shallow electron trapping in band-tail states at Si/SiO2 interfaces in metal-oxide-semiconductor (MOS) devices and demonstrate it on two MOS devices fabricated at different laboratories. Despite displaying similar low temperature (4.2 K) peak mobilities, our ESR data reveal a significant difference in the Si/SiO2 interface quality of these two devices, specifically an order of magnitude difference in the number of shallow trapped charges at the Si/SiO2 interfaces. Thus, our ESR method allows a quantitative evaluation of the Si/SiO2 interface quality at low electron densities, where conventional mobility measurements are not possible. [ABSTRACT FROM AUTHOR]

We have investigated the influence of Si–N complexes on the electronic properties of GaAsN alloys. The presence of Si–N complexes is suggested by a decrease in carrier concentration, n, with increasing N-composition, observed in GaAsN:Si films but not in modulation-doped heterostructures. In addition, for GaAsN:Te (GaAsN:Si), n increases substantially (minimally) with annealing-T, suggesting a competition between annealing-induced Si–N complex formation and a reduced concentration of N-related traps. Since Si–N complex formation is enhanced for GaAsN:Si growth with the (2×4) reconstruction, which has limited group V sites for As–N exchange, the (Si–N)As interstitial pair is identified as the dominant Si–N complex. [ABSTRACT FROM AUTHOR]

We have used rapid thermal annealing to investigate the influence of N interstitials on the electronic properties of GaAsN alloys. Nuclear reaction analysis reveals an annealing-induced decrease in the interstitial N concentration, while the total N composition remains constant. Corresponding signatures for the reduced interstitial N concentration are apparent in Raman spectra. Following annealing, both the room-T carrier concentration, n, and the mobility increase. At higher measurement-Ts, a thermally activated increase in n suggests the presence of a trap near GaAsN conduction band edge with activation energy 85±15 meV. The annealing-induced increase in n suggests the association of the trap with interstitial N. [ABSTRACT FROM AUTHOR]

High-fidelity single-shot readout of spin qubits requires distinguishing states much faster than the T1 time of the spin state. One approach to improving readout fidelity and bandwidth (BW) is cryogenic amplification, where the signal from the qubit is amplified before noise sources are introduced and room-temperature amplifiers can operate at lower gain and higher BW. We compare the performance of two cryogenic amplification circuits: a current-biased heterojunction bipolar transistor circuit (CB-HBT), and an AC-coupled HBT circuit (AC-HBT). Both circuits are mounted on the mixing-chamber stage of a dilution refrigerator and are connected to silicon metal oxide semiconductor (Si-MOS) quantum dot devices on a printed circuit board (PCB). The power dissipated by the CB-HBT ranges from 0.1 to 1 μW whereas the power of the AC-HBT ranges from 1 to 20 μW. Referred to the input, the noise spectral density is low for both circuits, in the 15 to 30 fA/ Hz range. The charge sensitivity for the CB-HBT and AC-HBT is 330 μe/ Hz and 400 μe/ Hz , respectively. For the single-shot readout performed, less than 10 μs is required for both circuits to achieve bit error rates below 10−3, which is a putative threshold for quantum error correction. [ABSTRACT FROM AUTHOR]