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This work presents a fast-locking and low-jitter fractional- ${N}$ bang-bang phase-locked loop (BBPLL). To break the trade-off between jitter and locking time which is typical of BBPLLs, two novel techniques are introduced. A gear-shift technique, denoted as type-II gear-shift, avoids limit cycles in the phase-locked loop (PLL) frequency transient and optimizes the locking time of the main PLL loop. The adaptive frequency switching (AFS) technique reduces the PLL frequency error upon channel switching exploiting the already existing hardware. The prototype, implemented in a 28-nm CMOS process, has an active area of 0.23 mm2 and achieves a locking time always below 1.56 $\mu \text{s}$ (within 80 ppm accuracy) for frequency jumps up to 1.5 GHz over the 8.5–10 GHz tuning range. The measured rms jitter (integrated from 1 kHz to 100 MHz) is 48.6 fs for integer- $N$ channels and 68.6 fs for near-integer fractional- ${N}$ channels, with a worst case fractional spur of −58.2 dBc. The power consumption is 20 mW, leading to a jitter-power figure of merit of −253.2 and −250.3 dB for integer- $N$ and fractional- $N$ channels, respectively. [ABSTRACT FROM AUTHOR]