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Reference voltage/current generation is essential to the Analog circuit design. There have been several ways to generate quality reference voltage using bandgap reference (BGR) and there are mainly two types: current mode and voltage mode. The current-mode bandgap reference (CBGR) is widely accepted in industry due to having an output voltage which is below 1 V. However, its drawbacks include a lack of proportional to absolute temperature (PTAT) current availability, a large silicon area, multiple operating points, and a large temperature coefficient (TC). In this paper, various operating points are explained in detail with diagrams. Similar to the conventional voltage mode bandgap reference (VBGR) circuits, modifications of the existing circuits with only two operating points have also been proposed. Moreover, the proposed BGR occupies a much smaller area due to eliminating the complimentary to absolute temperature (CTAT) current-generating resistor. A new self-biased opamp was introduced to operate from a 1.05 V supply, reducing systematic offset and TC of the BGR. The proposed solution has been implemented in 28 nm CMOS TSMC technology, and extraction simulations were performed to prove the robustness of the proposed circuit. The targeted mean BGR output is 500 mV, and across the industrial temperature range (−40 to 125 °C), the simulated TC is approximately 10.5 ppm/°C. The integrated output noise within the observable frequency band is 19.6 µV (rms). A 200-point Monte Carlo simulation displays a histogram with a 2.6 mV accuracy of 1.2% (±3-sigma). The proposed BGR circuit consumes 32.8 µW of power from a 1.05 V supply in a fast process and hot (125 °C) corner. It occupies a silicon area of 81 × 42 µm (including capacitors). This design can aim for use in biomedical and sensor applications. [ABSTRACT FROM AUTHOR]

The object of this research was a self-resonated inverter, based on paralleled Insulated-Gate Bipolar Transistors (IGBTs), for high-frequency induction heating equipment, operating in a wide range of output powers, applicable for research and industrial purposes. For the nominal installed capacity for these types of invertors to be improved, the presented inverter with a modified circuit comprising IGBT transistors connected in parallel was explored. The suggested topology required several engineering problems to be solved: minimisation of the current mismatch amongst the paralleled transistors; a precise analysis of the dynamic and static transistors' parameters; determination of the derating and mismatch factors necessary for a reliable design; experimental verification confirming the applicability of the suggested topology in the investigated inverter. This paper presents the design and analysis of IGBT transistors based on datasheet parameters and mathematical apparatus application. The expected current mismatch and the necessary derating factor, based on the expected mismatch in transistor parameters in a production lot, were determined. The suggested design was experimentally tested and investigated using a self-resonant inverter model in a melting crucible induction laboratory furnace. [ABSTRACT FROM AUTHOR]

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65 nm CMOS technology. It results in 81 dB voltage gain, which is 21 dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8 V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1 V supply. The circuit draws a total static current of 295 μ A and occupies 5000 μ m2 of silicon area. [ABSTRACT FROM AUTHOR]

This paper presents a 65 nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5–100 mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loop-gain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25–50 dB gain, and post-layout simulations showed a 15 dB reduction in the harmonic distortion for 20 mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108 μ m2 silicon area and consumes 0.43  μ A from a 1.2 V power supply. [ABSTRACT FROM AUTHOR]

A compact high gain current mode instrumentation amplifier (IA) has been proposed for biomedical imaging applications. Conventional IAs rely on several matching resistors which occupies a lot of silicon area, the input and output common mode voltages are exactly same and the maximum applied signal amplitude is limited by internal node voltage swings. The present proposal eliminates the need for matching resistors by processing signals in the current mode. Hence input amplitudes are no longer limited by the voltage headroom and input and output common-mode voltages can be independent. An amplifier with a differential gain greater than 52 dB and a common mode rejection ratio greater than 120 dB has been implemented in 65 nm CMOS Technology and Post layout simulations were presented. The total circuit occupies 4500 μm2 silicon area and circuit consumes ~ 260 μA from 1.8 V power supply. [ABSTRACT FROM AUTHOR]

Intersection control has an important role in the management of urban traffic to ensure safety, high traffic flow and to prevent congestion. Recently, a growing body of literature has been reported on the theme of non-signalised intersection control in which traffic lights are replaced with intelligent road side units. Data from several studies suggest that non-signalised control could reduce vehicle delays and fuel consumption significantly whilst ensuring safety. However, there is little published data on the impact of the mixed driving behaviour with human-driven vehicles and autonomous vehicles. This paper investigates the emerging role of connectivity and vehicle autonomy in the context of traffic control under the mixed driving behaviour scenario. The concepts of vehicle-to-infrastructure (V2I) communications and multi-agent systems are central to achieving a robust and reliable traffic-light-free intersection control. Comprehensive computer simulation results on a four-way intersection indicate over 96% reduced average vehicle delay and 37% less fuel consumption with the non-signalised control solution compared to the traffic light control. The outcome of this study offers some important insights into enabling cooperation between vehicles and traffic infrastructure via V2I communications, in order to make more efficient real-time decisions about traffic conditions, whilst ensuring a higher degree of safety. [ABSTRACT FROM AUTHOR]

This paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65 nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130 μA from a 1.2 V power supply. [ABSTRACT FROM AUTHOR]

Capturing a near-perfect, artefact free signal is an ideal of biomedicine. However, this depends on the removal of different types of artefact, all of which can be considered unwanted noise on the desired signal. Failure to remove artefacts could lead to a clinical misinterpretation of the results. All medical equipment such as electrocardiogram systems which use electrodes attached to patients suffer from artefacts, with effects ranging from minor blurring to significant distortion of the output signal(s). For this reason, it is important to identify how artefacts can influence the output signal. In this paper, we propose a new technique to detect and minimise movement artefacts using strain gauges embedded into the electrodes. [ABSTRACT FROM AUTHOR]

The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of − 62 dB has been achieved with 7 mV pk-pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um2 silicon area. [ABSTRACT FROM AUTHOR]

This paper proposes a technique to detect Leukaemia (blood cancer) based on the frequency modulation of a relaxation oscillator by changes in the dielectric constant of blood cells. A novel 16-bit frequency detector with a digital output has been proposed to detect the frequency difference between two oscillators based on healthy blood and Leukaemic blood. A circuit has been designed, to operate on a 1.2 V supply, post layout simulations shows 0.35 mA current consumption. The chip Area including pads ~0.6 mm × 0.45 mm. [ABSTRACT FROM AUTHOR]

This paper presents a self-calibration technique for the removal of measurement errors caused by thermal gradients in thermopile-based infrared thermometry, particularly when measuring low temperatures. Applications for this self-calibration method include low-temperature measurement in the food industry and infrared thermometers for remote temperature monitoring in cold climates. The self-calibration technique reported in this paper is shown to reduce the measurement error to within \pm 1\ ^\circ\C within 5 s of an extreme thermal shock, compared with an uncompensated thermometer that does not recover until the thermal gradient is removed. The root-mean-square temperature noise for the duration of the thermal shock test is less than 0.2 ^\circ\C. This technique is the subject of a patent application and can be applied to any infrared thermometer utilizing a thermopile, regardless of the thermopile size and geometry. [ABSTRACT FROM AUTHOR]

A transformer-less Buck-Boost direct current–direct current (DC–DC) converter in use for the fast charge of electric vehicles, based on powerful high-voltage isolated gate bipolar transistor (IGBT) modules is analyzed, designed and experimentally verified. The main advantages of this topology are: simple structure on the converter's power stage; a wide range of the output voltage, capable of supporting contemporary vehicles' on-board battery packs; efficiency; and power density accepted to be high enough for such a class of hard-switched converters. A precise estimation of the loss, dissipated in the converter's basic modes of operation Buck, Boost, and Buck-Boost is presented. The analysis shows an approach of loss minimization, based on switching frequency reduction during the Buck-Boost operation mode. Such a technique guarantees stable thermal characteristics during the entire operation, i.e., battery charge cycle. As the Buck-Boost mode takes place when Buck and Boost modes cannot support the output voltage, operating as a combination of them, it can be considered as critically dependent on the characteristics of the semiconductors. With this, the necessary duty cycle and voltage range, determined with respect to the input-output voltages and power losses, require an additional study to be conducted. Additionally, the tolerance of the applied switching frequencies for the most versatile silicon-based powerful IGBT modules is analyzed and experimentally verified. Finally, several important characteristics, such as transients during switch-on and switch-off, IGBTs' voltage tails, critical duty cycles, etc., are depicted experimentally with oscillograms, obtained by an experimental model. [ABSTRACT FROM AUTHOR]