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An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise highfrequency resolution PLL, and digital image rejection. To our knowledge this is the first reported multichannel broadband tuner embedded in a DOCSIS 3.0 System on a chip implemented in 65 nm pure digital CMOS technology. [ABSTRACT FROM AUTHOR]

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology. [ABSTRACT FROM AUTHOR]

The design and implementation of a baseband wide-band code-division multiple access (WCDMA) dual-antenna mobile terminal system-on-a-chip (SoC) is presented in this paper. Spatial diversity processing mitigates wireless channel impairments and is a key enabling technology for WCDMA to support high quality of service at high data rates and capacity. The SoC integrates the baseband transceiver, coding and decoding functions, microcontrollers to implement the radio access protocols, and external interfaces to communicate with the application layer. The receiver design, which takes advantage of diversity benefits in several blocks, is described in detail. The SoC was fabricated in a 0.18-μm 1.8-V CMOS technology and requires a total area of 72 mm consuming 532 mW at the maximum data rates. The application-specific integrated circuit was used in lab testing where a gain of up to 9 dB was observed for the dual-antenna receiver, which demonstrates the tremendous improvement provided by spatial diversity. The results presented in this paper provide a base architecture and a performance benchmark for commercial implementations of WCDMA mobile terminals. [ABSTRACT FROM AUTHOR]

This paper presents a complete study and characterization of a real-time frequency-hopped, frequency shift-keyed testbed capable of transmitting data at 160 kb/s, with hopping rates of up to 80 Khops/s operating in the 900 MHz band. The system provides the highest hopping rate reported to date and sets a new trend for FHSS communications with superior low probability of interception/detection and anti-jamming (LPI/LPD/AJ) capabilities. The architecture features a direct digital frequency synthesizer to enable high-rate hopping, and a frequency correlator-based demodulator, plus all digital timing and frequency recovery algorithms to minimize complexity. Furthermore, single sideband modulation was used to achieve spectral efficiency. The testbed is software configured and provides the user with full control over the diversity combining techniques, symbol interleaving, packet structure, and acquisition protocols. A total of 5850 independent experiments were carried out under various receiver configurations and wireless environments. The results underscore the dramatic potential for a system that optimally combines high-rate hopping, interleaving, and equal gain combining to combat severe propagation conditions, including multipath fading and intentional jamming. [ABSTRACT FROM AUTHOR]