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Background: In this study, we expand the supportive evidence for total disc arthroplasty (TDA) with results up to 21 years in a large patient cohort who received a semiconstrained ball-and-socket lumbar prosthesis. The objectives of the study were to compare the results for 1 versus 2-level surgeries and to evaluate whether prior surgery at the index level(s) impacts clinical outcomes. Methods: From 1999 to 2013, 1,187 patients with chronic lumbar degenerative disc disease (DDD) underwent lumbar TDA, of whom 772 underwent a 1-level procedure and 415 underwent a 2-level procedure. A total of 373 (31.4%) of the 1,187 patients had prior index-level surgery. Patients were evaluated preoperatively; at 3, 6, 12, 18, and 24 months postoperatively; and yearly thereafter. The follow-up duration ranged from 7 to 21 years (mean, 11 years and 8 months). Collected data included radiographic, neurological, and physical assessments, as well as self-evaluations using the Oswestry Disability Index (ODI) and visual analog scale (VAS) for back and leg pain. Perioperative data points, complication rates, and reoperation or revision rates were also assessed. Patients were divided into 4 groups: 1-level TDA with no prior surgery at the index level, 1-level TDA with prior surgery, 2-level TDA with no prior surgery, and 2-level TDA with prior surgery. Results: All groups showed dramatic reduction in the ODI at 3 months postoperatively and maintained these scores over time. Although VAS pain did not diminish to its final level as rapidly for patients with prior surgery, there was no significant difference between the groups in terms of pain reduction at 24 months postoperatively. Of 1,187 patients, 49 (4.13%) required either a new surgery at another level or revision or reoperation at the index level. Rates were too low in all groups to compare them statistically. Total TDA revision and adjacent-level surgery rates over 7 to 21 years were very low (0.67% and 1.85%, respectively). Conclusions: This study demonstrates the robust long-term clinical success of 1 and 2-level lumbar TDA as assessed at 7 to 21 years postoperatively in one of the largest evaluated cohorts of patients with TDA. Patients had dramatic and maintained reductions in disability and pain scores over time and low rates of index-level revision or reoperation and adjacent-level surgery relative to published long-term fusion data. Additionally, patients who underwent 1-level lumbar TDA and those who underwent 2-level TDA demonstrated equivalent improvement, as did patients with prior surgery at the index level and those with no prior surgery. Level of Evidence: Therapeutic Level III. See Instructions for Authors for a complete description of levels of evidence. [ABSTRACT FROM AUTHOR]

Radar processing via spiking neural networks (SNNs) has recently emerged as a solution in the field of ultralow-power wireless human–computer interaction. Compared to traditional energy- and area-hungry deep learning methods, SNNs are significantly more energy-efficient and can be deployed in the growing number of compact SNN accelerator chips, making them a better solution for ubiquitous IoT applications. We propose a novel SNN strategy for radar gesture recognition, achieving more than 91% of accuracy on two different radar datasets. Our work significantly differs from previous approaches as: 1) we use a novel radar-SNN training strategy; 2) we use quantized weights, enabling power-efficient implementation in real-world SNN hardware; and 3) we report the SNN energy consumption per classification, clearly demonstrating the real-world feasibility and power savings induced by SNN-based radar processing. We release an evaluation code to help future research. [ABSTRACT FROM AUTHOR]

A CMOS image sensor (CIS) is presented, simultaneously achieving low noise and high frame rate. The imager innovatively employs column-parallel dual-slope (DS) integrating analog-to-digital converters (ADCs) based on a phase-delay-counting principle and using oversampling to suppress the readout thermal noise. A noise analysis of the DS-integrating ADC in correlated-double-sampling operation is provided to prove the low-noise advantage of the proposed architecture. Furthermore, the design considerations of the presented architecture are derived based on the analysis of nonideality effects. Based on these analytical results, design tradeoffs are discussed and applied in the test chip. The test chip, fabricated in a 4M1P 0.18- \mu \textm CIS technology, contains a 128 \times 128 pixel array. The measurement results show that each of the 128 column-level ADCs converts a pixel in 3.8 \mu \text{s} and achieves a noise floor of 1\text {e}^{-}_{\mathrm{ rms}}$ . The chip consumes 49 mW excluding the I/O power and 59 mW including the I/O power, resulting in a very good figure of merit value of 1.4 and 1.7 [e−.nJ], respectively. [ABSTRACT FROM AUTHOR]

A new circularly polarized wire-grid nano-antenna array designed for optical telecommunication applications is proposed in this paper. The array consists of two groups of radiators, which are orthogonal to each other. Each group consists of six aligned radiators connected via nonradiating connectors. A 90° phase shift is achieved by inserting a gap between the feeding coupling rods and the inner radiators of one of the two antenna groups. The antenna is characterized by its high directivity (10.8 dBi) and a wide axial ratio bandwidth, which covers the range from 188.2 to 197.8 THz. The radiation efficiency of the antenna is 82.75% at 193.55 THz with very small variations along its operating bandwidth. Such good radiation characteristics are very attractive for optical communication applications. [ABSTRACT FROM PUBLISHER]

The finite volume discretization of nonlinear elasticity equations seems to be a promising alternative to the traditional finite element discretization as mentioned by Lee et al. [Computers and Structures (2013)]. In this work, we propose to solve the elastic response of a solid material by using a cell-centered finite volume Lagrangian scheme in the current configuration. The hyperelastic approach is chosen for representing elastic isotropic materials. In this way, the constitutive law is based on the principle of frame indifference and thermodynamic consistency, which are imposed by mean of the Coleman-Noll procedure. It results in defining the Cauchy stress tensor as the derivative of the free energy with respect to the left Cauchy-Green tensor. Moreover, the materials being isotropic, the free-energy is function of the left Cauchy-Green tensor invariants, which enable the use of the neo-Hookean model. The hyperelasticity system is discretized using the cell-centered Lagrangian scheme from the work of Maire et al. [J. Comput. Phys. (2009)]. The 3D scheme is first order in space and time and is assessed against three test cases with both infinitesimal displacements and large deformations to show the good accordance between the numerical solutions and the analytic ones. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A scalable time-based analog front end in 40-nm CMOS is presented for ECG readout for ambulatory applications. The main challenge addressed is achieving a large dynamic range readout (necessary to handle large signals during motion) in a power and area-efficient manner at low voltage supplies while also tackling the challenges of increase in flicker noise and gate-leakage current. Demonstrated results show a significant improvement in ac-dynamic range without compromising on area (0.015 mm ^2 ) and power consumption ( 3.3~\mu \textW ). This paper will be relevant toward developing low-cost, low-power sensor system-on-chips required for wearable biomedical applications. [ABSTRACT FROM AUTHOR]

This work presents a general framework that enables one to compute near- and far-field interactions inside a circuit simulator environment, aimed at efficient system-level electromagnetic compatibility (EMC) analysis. For readability, the paper is subdivided in two parts. Part I focuses on deriving (high-order) spherical wave based macromodels in optimal time and describes two truncation criteria which define the maximum complexity of the models. The latter is generally a compromise between the accuracy of reconstructed near-fields and the computation time for evaluating interactions between these models, and is therefore a crucial parameter when such models are to be applied in fast circuit solvers. Existing guidelines on truncating spherical wave expansions are held against the newly derived criteria. In part II, the framework is extended with optimized routines that enable one to compute efficiently near- and far-field interactions between the macromodels discussed in part I. It will be shown that by extensive understanding of spherical wave expansions, the underlying computations only add negligible computational cost compared to traditional S-parameter simulations, partially contributed to correctly chosen truncations of the applied models. [ABSTRACT FROM PUBLISHER]

In this second part of two papers, the framework presented in Part I is extended with optimized routines that enable one to evaluate interactions between several devices under test (DUTs) through free space inside a circuit simulator environment, aimed at efficient system-level electromagnetic compatibility (EMC) analysis. Using a generalized scattering matrix formulation and an extensive understanding of the underlying theory of spherical wave expansions (SWEs), it is shown that the presented routines only add negligible computational cost to traditional scattering parameter simulations. The latter is obtained on the one hand by optimally truncating SWE based macromodels as described in Part I and on the other hand by observing that both near- and far-field interactions are only determined by a subset of parameters in the models. Therefore, this paper derives guidelines on the number of parameters needed to assure accurate simulations and validates them using two applications: 1) computing the radiated coupling between two DUTs; and 2) extending the first example in order to simulate efficiently a cylindrical scan of a DUT by an arbitrary measurement antenna. [ABSTRACT FROM PUBLISHER]

A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented. With the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high power efficiency are achieved. The nonlinearities of the coarse and the fine VCO-based quantizers are mitigated by distortion cancellation and voltage swing reduction schemes respectively. Because of the intrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The experimental results in 40 nm CMOS show that, with 1.6 GHz sampling frequency, the proposed ADC reaches 59.5 dB SNDR and 67.7 dB SFDR for 40 MHz bandwidth. The power consumption is only 2.57 mW under 0.9 V power supply, corresponding the best FoM (42 fJ/step) among high bandwidth (>20 MHz) DS ADCs. [ABSTRACT FROM AUTHOR]

Surrogate model assisted evolutionary algorithms (SAEAs) have recently attracted much attention due to the growing need for computationally expensive optimization in many real-world applications. Most current SAEAs, however, focus on small-scale problems. SAEAs for medium-scale problems (i.e., 20–50 decision variables) have not yet been well studied. In this paper, a Gaussian process surrogate model assisted evolutionary algorithm for medium-scale computationally expensive optimization problems (GPEME) is proposed and investigated. Its major components are a surrogate model-aware search mechanism for expensive optimization problems when a high-quality surrogate model is difficult to build and dimension reduction techniques for tackling the “curse of dimensionality.” A new framework is developed and used in GPEME, which carefully coordinates the surrogate modeling and the evolutionary search, so that the search can focus on a small promising area and is supported by the constructed surrogate model. Sammon mapping is introduced to transform the decision variables from tens of dimensions to a few dimensions, in order to take advantage of Gaussian process surrogate modeling in a low-dimensional space. Empirical studies on benchmark problems with 20, 30, and 50 variables and a real-world power amplifier design automation problem with 17 variables show the high efficiency and effectiveness of GPEME. Compared to three state-of-the-art SAEAs, better or similar solutions can be obtained with 12% to 50% exact function evaluations. [ABSTRACT FROM PUBLISHER]

The design and optimization (both sizing and layout) of mm-wave integrated circuits (ICs) have attracted much attention due to the growing demand in industry. However, available manual design and synthesis methods suffer from a high dependence on design experience, being inefficient or not general enough. To address this problem, a new method, called general mm-wave IC synthesis based on Gaussian process model assisted differential evolution (GASPAD), is proposed in this paper. A medium-scale computationally expensive constrained optimization problem must be solved for the targeted mm-wave IC design problem. Besides the basic techniques of using a global optimization algorithm to obtain highly optimized design solutions and using surrogate models to obtain a high efficiency, a surrogate model-aware search mechanism (SMAS) for tackling the several tens of design variables (medium scale) and a method to appropriately integrate constraint handling techniques into SMAS for tackling the multiple (high-) performance specifications are proposed. Experiments on two 60 GHz power amplifiers in a 65 nm CMOS technology and two mathematical benchmark problems are carried out. Comparisons with the state-of-art provide evidence of the important advantages of GASPAD in terms of solution quality and efficiency. [ABSTRACT FROM PUBLISHER]

Neural probes have become the most important tool for enabling neuroscientists to place microelectrode sensors close to individual neurons and to monitor their activity in vivo. With such devices, it is possible to perform acute or chronic extracellular recordings of electrical activity from a single neuron or from groups of neurons. After the many developments in neural implants, it has become clear that large arrays of electrodes are desirable to further investigate the activity performed by complex neural networks. Therefore, in this paper, we propose a CMOS neural probe containing 455 active electrodes in the probe shank (100 \mum wide, 10 mm long, and 50 \mum thick) and 52 simultaneous readout channels in the probe body (2.9\,\times\,3.3 mm^2). In situ amplification under each electrode enables low-impedance interconnection lines, regardless of the electrode impedance, with a residual crosstalk of -44.8 dB. This design has been implemented in a 0.18-\mum standard CMOS technology, with additional CMOS-compatible post-processing performed at wafer level to define the electrodes and the probe outline. In this architecture, the analog front-end achieves an input-referred noise of 3.2 \mu \Vrms and an NEF of 3.08. The power consumption of the core circuit is 949.8 \muW, while the total power consumption is 1.45 mW. The high-density active-electrode array in this neural probe allows for the massive recording of neural activity. In vivo measurements demonstrate successful simultaneous recordings from many individual cells. [ABSTRACT FROM PUBLISHER]

In engineering design and manufacturing optimization, the trade-off between a quality performance metric and the probability of satisfying all performance specifications (yield) of a product naturally leads to a chance-constrained bi-objective stochastic optimization problem (CBSOP). A new method, called MOOLP (multi-objective uncertain optimization with ordinal optimization (OO)), Latin supercube sampling and parallel computation), is proposed in this paper for dealing with the CBSOP. This proposed method consists of a constraint satisfaction phase and an objective optimization phase. In its constraint satisfaction phase, by using the OO technique, an adequate number of samples are allocated to promising solutions, and the number of unnecessary MC simulations for noncritical solutions can be reduced. This can achieve more than five times speed enhancement compared to the application of using an equal number of samples for each candidate solution. In its MOEA/D-based objective optimization phase, by using LSS, more than five times speed enhancement can be achieved with the same estimation accuracy compared to primitive MC simulation. Parallel computation is also used for speedup. A real-world problem of the bi-objective variation-aware sizing for an analog integrated circuit is used in this paper as a practical application. The experiments clearly demonstrate the advantages of MOOLP. [ABSTRACT FROM AUTHOR]

In this paper, an efficient reciprocity-based algorithm is proposed to predict the worst case voltages and currents induced by external plane waves at the ports of a multiconductor transmission-line system. The proposed algorithm consists of two main steps. In the first step, the far-field radiation of the multiconductor transmission-line system is fully characterized by a minimal number of full-wave simulations. In the second step, this information is used to efficiently evaluate the voltages and currents induced by a plane wave with arbitrary angles of incidence and polarization. After this, their worst case values can be easily found. The main advantage of the proposed algorithm is that no new full-wave simulations are required if different incoming plane waves or different sets of terminations at the ports of the multiconductor transmission-line system are to be considered. [ABSTRACT FROM AUTHOR]

Existing radio frequency (RF) integrated circuit (IC) design automation methods focus on the synthesis of circuits at a few GHz, typically less than 10 GHz. That framework is difficult to apply to RF IC synthesis at mm-wave frequencies (e.g., 60–100 GHz). In this paper, a new method, called efficient machine learning-based differential evolution, is presented for mm-wave frequency linear RF amplifier synthesis. By using electromagnetic (EM) simulations to evaluate the key passive components, the evaluation of circuit performances is accurate and solves the limitations of parasitic-included equivalent circuit models and predefined layout templates used in the existing synthesis framework. A decomposition method separates the design variables that require expensive EM simulations and the variables that only need cheap circuit simulations. Hence, a low-dimensional expensive optimization problem is generated. By the newly proposed core algorithm integrating adaptive population generation, naive Bayes classification, Gaussian process and differential evolution, the generated low-dimensional expensive optimization problem can be solved efficiently (by the online surrogate model), and global search (by evolutionary computation) can be achieved. A 100 GHz three-stage differential amplifier is synthesized in a 90 nm CMOS technology. The power gain reaches 10 dB with more than 20 GHz bandwidth. The synthesis costs only 25 h, having a comparable result and a nine times speed enhancement compared with directly using the EM simulator and global optimization algorithms. [ABSTRACT FROM PUBLISHER]

State-of-the-art synthesis methods for microwave passive components suffer from the following drawbacks. They either have good efficiency but highly depend on the accuracy of the equivalent circuit models, which may fail the synthesis when the frequency is high, or they fully depend on electromagnetic (EM) simulations, with a high solution quality but are too time consuming. To address the problem of combining high solution quality and good efficiency, a new method, called memetic machine learning-based differential evolution (MMLDE), is presented. The key idea of MMLDE is the proposed online surrogate model-based memetic evolutionary optimization mechanism, whose training data are generated adaptively in the optimization process. In particular, by using the differential evolution algorithm as the optimization kernel and EM simulation as the performance evaluation method, high-quality solutions can be obtained. By using Gaussian process and artificial neural network in the proposed search mechanism, surrogate models are constructed online to predict the performances, saving a lot of expensive EM simulations. Compared with available methods with the best solution quality, MMLDE can obtain comparable results, and has approximately a tenfold improvement in computational efficiency, which makes the computational time for optimized component synthesis acceptable. Moreover, unlike many available methods, MMLDE does not need any equivalent circuit models or any coarse-mesh EM models. Experiments of 60 GHz syntheses and comparisons with the state-of-art methods provide evidence of the important advantages of MMLDE. [ABSTRACT FROM AUTHOR]

This paper presents MOJITO, a system that performs structural synthesis of analog circuits, returning designs that are trustworthy by construction. The search space is defined by a set of expert-specified, trusted, hierarchically-organized analog building blocks, which are organized as a parameterized context-free grammar. The search algorithm is a multiobjective evolutionary algorithm that uses an age-layered population structure to balance exploration versus exploitation. It is validated with experiments to search across >100000 different one-stage and two-stage opamp topologies, returning human-competitive results. The runtime is orders of magnitude faster than open-ended systems, and unlike the other evolutionary algorithm approaches, the resulting circuits are trustworthy by construction. The approach generalizes to other problem domains which have accumulated structural domain knowledge, such as robotic structures, car assemblies, and modeling biological systems. [ABSTRACT FROM AUTHOR]

In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and response-surface-based yield optimization methods face challenges in accuracy. Monte-Carlo (MC) simulation is general and accurate for yield estimation, but its efficiency is not high enough to make MC-based analog yield optimization, which requires many yield estimations, practical. In this paper, techniques inspired by computational intelligence are used to speed up yield optimization without sacrificing accuracy. A new sampling-based yield optimization approach, which determines the device sizes to optimize yield, is presented, called the ordinal optimization (OO)-based random-scale differential evolution (ORDE) algorithm. By proposing a two-stage estimation flow and introducing the OO technique in the first stage, sufficient samples are allocated to promising solutions, and repeated MC simulations of non-critical solutions are avoided. By the proposed evolutionary algorithm that uses differential evolution for global search and a random-scale mutation operator for fine tunings, the convergence speed of the yield optimization can be enhanced significantly. With the same accuracy, the resulting ORDE algorithm can achieve approximately a tenfold improvement in computational effort compared to an improved MC-based yield optimization algorithm integrating the infeasible sampling and Latin-hypercube sampling techniques. Furthermore, ORDE is extended from plain yield optimization to process-variation-aware single-objective circuit sizing. [ABSTRACT FROM AUTHOR]