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A Sigma-Delta modulator (SDM) realized with a fully differential third-order single-loop cascaded integrator feedforward (CIFF) architecture is proposed. A pair of low-frequency chopper switches are nested outside the chopper amplifier to further reduce the residual offset voltage. To reduce the power consumption and ensure linearity, a high-speed dynamic comparator is also used to implement a one-bit quantizer. The proposed architecture and the corresponding functionality are first simulated in MATLAB Simulink at the behavioral level. The results show that the designed modulator has an SNDR of 124.9 dB corresponding to an ENOB of 20.46 bits at a clock frequency of 256 kHz and 312.5 Hz input with a differential-mode voltage of 700 mV sinusoidal waveform. Based on SMIC 180 nm/1.8 V standard CMOS process on the Cadence platform, the subcircuit-level simulation is also performed, while the result shows that the proposed modulator can effectively achieve 115.52 dB SNDR, 18.90-bit ENOB, and 8.40 mW power consumption, which correspond to FoM W and FoM schreier of 0.067 pJ/step and 163.27 dB, respectively. The proposed modulator shows a significant advantage to be applied for high-precision analog-to-digital conversion applications such as high-quality equipment for audio, ECG and EEG signal sensing. [ABSTRACT FROM AUTHOR]

Temperature dependence of the low‐frequency electronic noise in NiOx/β‐Ga2O3 p–n heterojunction diodes is reported. The noise spectral density is of the 1/f‐type near room temperature but shows signatures of Lorentzian components at elevated temperatures and at higher current levels (f is the frequency). It is observed that there is an intriguing non‐monotonic dependence of the noise on temperature near T = 380 K. The Raman spectroscopy of the device structure suggests material changes, which results in reduced noise above this temperature. The normalized noise spectral density in such diodes is determined to be on the order of 10−14 cm2 Hz−1 (f = 10 Hz) at 0.1 A cm−2 current density. In terms of the noise level, NiOx/β‐Ga2O3 p–n diodes perform excellently for new technology and occupy an intermediate position among devices of various designs implemented with different ultra‐wide‐bandgap semiconductors. The obtained results are important for understanding the electronic properties of NiOx/β‐Ga2O3 heterojunctions and contribute to the development of noise spectroscopy as the quality assessment tool for new electronic materials and device technologies. [ABSTRACT FROM AUTHOR]

The elementary jumps in the electron current through conducting filaments of two nanometer-sized virtual memristor structures consisting of a contact of a conductive atomic force microscope probe to the Si3N4 layer with the thickness of 6 nm deposited onto the n + + -Si(001) conductive substrates are investigated. These structures are: (S1) the Si3N4/Si film; (S2) the Si3N4/SiO2/Si stack, a similar structure with 2 nm SiO2 sublayer between the film and the substrate. Usually, such investigations are performed by the analysis of the waveform of this current with the aim of extracting the random telegraph noise (RTN). Here, we develop a new indirect method, which is based on the measurement of the spectrum of the low-frequency flicker noise in the current without extracting the RTN. We propose that the flicker noise is caused by the motion (drift/diffusion) of nitrogen ions via vacancies within and around the filament. The number of these ions is estimated by taking into account the geometrical parameters of the filament. This allows us to estimate the root mean square magnitude i 0 of the current jumps, which are caused by random jumps of nitrogen ions, and the number M of these ions. This is fundamental for understanding the elementary mechanisms of the electron current flowing through the filament and the resistive switching in memristor devices. [ABSTRACT FROM AUTHOR]

We discuss the implementation challenges of gas sensing systems based on low-frequency noise measurements on chemoresistive sensors. Resistance fluctuations in various gas sensing materials, in a frequency range typically up to a few kHz, can enhance gas sensing by considering its intensity and the slope of power spectral density. The issues of low-frequency noise measurements in resistive gas sensors, specifically in two-dimensional materials exhibiting gas-sensing properties, are considered. We present measurement setups and noise-processing methods for gas detection. The chemoresistive sensors show various DC resistances requiring different flicker noise measurement approaches. Separate noise measurement setups are used for resistances up to a few hundred kΩ and for resistances with much higher values. Noise measurements in highly resistive materials (e.g., MoS2, WS2, and ZrS3) are prone to external interferences but can be modulated using temperature or light irradiation for enhanced sensing. Therefore, such materials are of considerable interest for gas sensing. [ABSTRACT FROM AUTHOR]

This article continues a series of publications by the authors with the results of studying the variations in electrical resistivity in four layers of the geoelectric section. Precision soundings using the VES method have been carried out on a stationary multielectrode array with a maximum spacing of the supply electrodes of 3 km in the central part of the Garm geophysical test site in Tajikistan daily for 12 years. As a result of observations, a profile containing about 4500 pickets was obtained. Unlike conventional soundings, each picket of this profile corresponds not to a geographic point, but to a certain point in time. For the inversion of the time profile, specially developed precision algorithms with additional regularization of the inverse problem are used. The solution error is controlled by numerical simulation methods, during which the direct and then the inverse VES problem is solved first for profiles simulating the experimental profile, and the actual solution errors are estimated. Analysis has shown that the error in calculating the seasonal component of resistivity variations in layers 1–4 is 1–2%, and the error for flicker noise is from 1.3 to 3%. In this case, the total amplitude of seasonal variations in resistivity in the upper layer is more than 50%, and in the second layer it is 5.5%; the amplitude of variations in flicker-noise components for the same layers is estimated as 54 and 24%, respectively. In this paper we analyze the effect of external (exogenous) factors on resistivity variations at different depths. The fact of a significant effect of the groundwater level and soil temperature on the resistivity of the upper layer of the section with a thickness of 1.5 m has been established. For temperature, the coefficient of proportionality averaged over the entire layer is –0.58 ± 0.12%/deg, for the groundwater level, it is –0.8%/cm. For the second layer of the section (depth 1.5–10.2 m), an exact coincidence of the form of the seasonal variation of resistivity and atmospheric pressure is found. This coincidence is not accidental, since both atmospheric pressure and resistivity in layer 2 are characterized by an anomalous form of seasonal variation with two maxima and two minima during the year, which is completely atypical for seasonal changes in resistivity. At the same time, for relatively higher frequency (HF) variations (periods from several days to several weeks), there is no correlation effect. The authors attribute the possible reason for the observed effect to pressure regulation of competitive sources of groundwater inflow into the aquifer confined to the second layer of the section. It is assumed that the salinity and conductivity of water in competing sources differ sharply, which is quite plausible from geological considerations. Changes in atmospheric pressure change the inflow of water from these two sources, which leads to a change in the conductivity of the layer. The inertia of water exchange processes determines the absence of dependence of resistivity on atmospheric pressure at relatively high frequencies and the presence of such a relationship for variations with a characteristic duration of more than a month. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) is widely known for its high error tolerance and efficient computing ability of complex functions with remarkably simple logic gates. The noise of electronic devices is widely used to be the entropy source due to its randomness. Compared with thermal noise and random telegraph noise (RTN), flicker noise is favored by researchers because of its high noise density. Meanwhile, unlike using RRAM, PCRAM and other emerging memory devices as the entropy source, using logic devices does not require any additional process steps, which is significant for industrialization. In this work, we systematically and statistically studied the 1/f noise characteristics of 14 nm FinFET, and found that miniaturizing the channel area of the device or lowering the ambient temperature can effectively increase the 1/f noise density of the device. This is of great importance to improve the accuracy of the SC system and simplify the complexity of the stochastic number generator (SNG) circuit. At the same time, these rules of 1/f noise characteristics in FinFET devices can provide good guidance for our device selection in circuit design. [ABSTRACT FROM AUTHOR]

In this work, the degradation of the random telegraph noise (RTN) and the threshold voltage ( V t ) shift of an 8.3Mpixel stacked CMOS image sensor (CIS) under hot carrier injection (HCI) stress are investigated. We report for the first time the significant statistical differences between these two device aging phenomena. The V t shift is relatively uniform among all the devices and gradually evolves over time. By contrast, the RTN degradation is evidently abrupt and random in nature and only happens to a small percentage of devices. The generation of new RTN traps by HCI during times of stress is demonstrated both statistically and on the individual device level. An improved method is developed to identify RTN devices with degenerate amplitude histograms. [ABSTRACT FROM AUTHOR]

This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce jitter variations, minimize oscillator spurious signals, and eliminate periodical phase error, a double edge-injection (window injection) scheme with synchronized edge directions is proposed. A combinational edge generator is utilized to substitute the sequential edge generators for injection timing requirements relaxation. By biasing devices in deep triode, digitally controlled delay cells currents are adopted for frequency tuning. This helps reducing the devices flicker (1/f) noise and minimize the DCRO overall phase noise. At 1 MHz offset of frequency, the proposed oscillator has a measured phase noise of −125.95 dBc/Hz and −115.6 dBc/Hz at oscillation frequencies of 913.4 MHz and 432.6 MHz, respectively. Fabricated in 350 nm CMOS process, with a maximum power consumption of 3.3 mW, and oscillating at 913.4 MHz, this DCRO achieves a tuned oscillator figure of merit (FoM) of −197.35 dBc/Hz. The core area of this edge-injection-based DRCO is only 0.08 mm2. [ABSTRACT FROM AUTHOR]

We describe challenges encountered in the design of continuoustime delta-sigma modulators that target high resolution (>16 bits) over wide bandwidths (several hundreds of kHz). The linearity of the feedback DAC and flicker noise introduced by the loop filter are primary problems that need to be addressed. We describe two techniques that are inherently more linear than prior-art DACs, namely the virtual-ground-switched resistor DAC and the zapped virtual-ground-switched dual return-to-open DAC. Flicker noise can be eliminated by chopping, but one needs to pay careful attention to minimize chopping artifacts. Example multi-bit and singlebit designs achieving in excess of 100 dB SNDR over a 250 kHz bandwidth, designed in a 180 nm CMOS technology, are used to illustrate the efficacy of the techniques described in this article. [ABSTRACT FROM AUTHOR]

A coupling mechanism between flicker noise and hot carrier degradation (HCD) is revealed in this work. Predicting the flicker noise properties of fresh and aged devices is becoming essential for circuit designs, requiring an understanding of the fundamental noise behaviors. While certain models for fresh devices have been proposed, those for aged devices have not been reported yet because of the lack of a clear mechanism. The flicker noise of aged FinFETs is characterized based on the measure-stress-measure (MSM) method and analyzed from the device physics. It is found that both the mean and deviations of the noise power spectral density increase compared with the fresh counterparts. A coupling mechanism is proposed to explain the trap time constants, leading to the trap characterizations in their energy profiles. The amplitude and number of contributing traps are also changing and are dependent on the mode of HCD and determined by the position of the induced traps. A microscopic picture is developed from the perspective of trap coupling, reproducing well the measured noise of advanced nanoscale FinFETs. The finding is important for accurate flicker noise calculations and aging-aware circuit designs. [ABSTRACT FROM AUTHOR]

The noise behavior of a proposed Ge-source counter-doped pocket-based double-gate tunnel FET (GS-PNPN-TFET) in the presence and absence of interfacial trap charge conditions is presented. The noise behavior was studied in terms of drain current noise power spectral density (Sid, unit A2/Hz) and gate voltage electron noise power spectral density (Svgee, unit V2/Hz) against variation of various device parameters, viz., body thickness (Tsi), pocket length (Lp), gate-oxide thickness (Tox), gate-oxide material, mole fraction, and doping density using Sentaurus TCAD software. Oxide–semiconductor interfacial trap charge of Gaussian distribution was used at two frequencies − 1 MHz and 10 GHz. Our analysis also includes the impact of temperature variation on noise. As per our findings, the noise spectrums are comparable for the presence and absence of interfacial trap charges in the proposed TFET. This is because the noise spectrum depends on on-current (ION) and the ION is negligibly influenced by the interfacial trap charges in the proposed TFET. However, off-current (IOFF) degrades when trap charges are present at the interface. In comparison with other FET devices, the proposed device offers improved Sid and Svgee values of roughly 1.82 × 10–29 A2/Hz and 5.5 × 10–20 V2/Hz, respectively, at 10 GHz frequency. Furthermore, the diffusion noise predominates at higher frequencies, while the generation–recombination noise is found to be dominant at low frequencies, as expected. Flicker noise is most noticeable at low and medium frequencies but fades away at higher frequencies. [ABSTRACT FROM AUTHOR]

Noises in the GPS vertical coordinate time series, mainly including the white and flicker noise, have been proven to impair the accuracy and reliability of GPS products. Various methods were adopted to weaken the white and flicker noises in the GPS time series, such as the complementary ensemble empirical mode decomposition (CEEMD), wavelet denoising (WD), and variational mode decomposition (VMD). However, a single method only works at a limited frequency band of the time series, and the corresponding denoising ability is insufficient, especially for the flicker noise. Hence, in this study, we try to build two combined methods: CEEMD & WD and VMD & WD, to weaken the flicker noise in the GPS positioning time series from the Crustal Movement Observation Network of China. First, we handled the original signal using CEEMD or VMD with the appropriate parameters. Then, the processed signal was further denoised by WD. The results show that the average flicker noise in the time series was reduced from 19.90 mm/year0.25 to 2.8 mm/year0.25. This relates to a reduction of 86% after applying the two methods to process the GPS data, which indicates our solutions outperform CEEMD by 6.84% and VMD by 16.88% in weakening the flicker noise, respectively. Those apparent decreases in the flicker noises for the two combined methods are attributed to the differences in the frequencies between the WD and the other two methods, which were verified by analyzing the power spectrum density (PSD). With the help of WD, CEEMD & WD and VMD & WD can identify more flicker noise hidden in the low-frequency signals obtained by CEEMD and VMD. Finally, we found that the two combined methods have almost identical effects on removing the flicker noise in the time series for 226 GPS stations in China, testified by the Wilcoxon rank sum test. [ABSTRACT FROM AUTHOR]

It is known that flicker noise is the most intriguing noise component because it can be found in any type of material, object, device, or system. Despite the struggle of scientists to find a mutual model for the 1/f flicker noise law, there is still a challenge to describe the law in many cases. Herein, the studies of two‐level random telegraph signal (RTS) fluctuations analyzed for the state‐of‐the‐art high‐electron‐mobility transistors (HEMTs), fabricated based on AlGaN/GaN heterostructures, are presented. It is revealed that the shape of the fluctuations can be used to describe the formation of a 1/fγ spectrum with γ = 1, 2, 3. The data demonstrate that the 1/f spectrum can be obtained as a result of the interactions of the carriers in parallel channels along the length of a system. Experimentally registered RTS fluctuations have a spectrum described by 1/fγ behavior. The data are in good agreement with the theoretically predicted pulsed shape, allowing the generation of a 1/f spectrum. Based on the data analysis and the theoretical description of the fluctuations, the origin of 1/f fluctuations in nonequilibrium conditions is explained by interactions resulting in correlations of carriers in two parallel channels as the common feature in the HEMT devices. [ABSTRACT FROM AUTHOR]

A detailed simulation-based investigation on the noise behavior of SiGe source-based Epitaxial layer Tunnel field effect transistor (SiGe source ETLTFET) and Silicon Synthetic Electric field TFET (Si-SETFET) in the presence of interface trap charges having Gaussian distribution is presented in this paper. The results demonstrated that the flicker and G-R noises dominate the noise characteristics at low frequencies, while diffusion noise is the major contributor at high frequencies for both devices. The drain current noise spectral density (Sid) behavior of SiGe source ETLTFET in the presence of trap shows a reduced value than Si-SETFET. The preceding argument is supported by the observation of normalised Sid (Sid/IDS2) vs Drain current (IDS). The value of net Sid for SiGe source ETLTFET is found to be ~10−26 A2/Hz till 1 MHz. Furthermore, noise analysis at various temperatures shows that noise in presence of trap charges has a greater influence at lower temperatures in the higher drain current region. The result also revealed that the the Sid vs. frequency variation is a decreasing function of the Ge mole fraction in SiGe source ETLTFET. A brief comparison of net Sid among some of the reported studies and this study has also been presented. SiGe source ETLTFET is found to be more noise immune over a wider frequency range in comparison to the state of the art devices. [ABSTRACT FROM AUTHOR]

Earlier, the authors carried out a unique experiment on long-term continuous precision monitoring of crustal resistivity variations in a highly seismic region. The result of this experiment can be considered a special type of VES profile, in which, instead of a linear coordinate, the sounding date changes from picket to picket. When processing precision monitoring data, it is necessary to solve the inverse VES problem with the highest possible accuracy. Standard programs for inversion of VES curves do not allow this, and even with very small fitting residuals, the actual error in reconstructing the resistivity can be huge due to equivalence effects. The authors have previously developed a special method for regularizing the residual functional, which multiply increases the accuracy in solving the inverse problem for the considered type of resistivity section, and a method for obtaining realistic, rather than underestimated estimates of the solution error. To do this, a package of synthetic resistivity profiles is formed that imitates a real section, the VES direct problem is solved, and time series of apparent resistivity are constructed, on which noise similar to real noise is superimposed. After that, the VES inverse problem is solved and the errors in reconstructing the model resistivity curves are analyzed. Such calculations were carried out both for the total signals and their components, obtained as a result of decomposition of the apparent resistivity series into physically determined components. The developed approach makes it possible to solve the inverse VES problem with heretofore unattainable accuracy. We emphasize that a reliable estimate of the solution errors is provided not by the convergence criteria of the inversion algorithm (they are almost always overly optimistic), but by direct calculations of the direct and inverse problems for synthetic profiles similar to real signals. In the present article, the profile of the experimental VES curves obtained in the course of this experiment is inverted. Series of resistivity variations are calculated in four layers of a geoelectric section with a duration of more than 12 years. It has been established that the upper layer of the section is characterized by trend and seasonal changes in resistivity with a large amplitude. Significant anomalous seasonal effects were found in the second layer of the section. For the third layer, the presence of small-amplitude seasonal effects was established, while there are no significant resistivity trends. Variations in the resistivity of the fourth layer are less reliably estimated; to detect the effects of external factors on electrical resistivity, it is necessary to use signal stacking methods. [ABSTRACT FROM AUTHOR]

As part of studies on the search for earthquake precursors, the authors have conducted an experiment on long-term precision monitoring of variations in the resistivity of the Earth's crust in a highly seismic region of Tajikistan. The primary data of this experiment can be considered a special type of VES profile, in which, instead of a linear coordinate, the sounding date changes from picket to picket. When processing precision monitoring data, it is necessary to solve the inverse VES problem with the highest possible accuracy. VES curve inversion programs commonly used in electric exploration do not allow this. The authors have previously developed a special method for regularizing the residual functional, which suppresses the effect of resistivity buildup, due to which the error in reconstructing the resistivity of rocks for profiles with a strong seasonal variation in resistivity is reduced by an order of magnitude. However, in some cases, the regularized algorithm strongly biases estimation of the amplitude of the seasonal resistivity variation in the lower layers of the section. In this paper, the operation of the proposed algorithm is tested in detail for nine model profiles simulating a real geoelectric section. The considered profiles differed in the characteristics of the seasonal variability of resistivity in the lower layers of the section (the phase and amplitude of seasonal effects varied). It is shown that resistivity buildup is effectively suppressed in all cases. For each model profile, the error in solving the inverse problem is estimated. The effect of a biased estimate of the amplitude of seasonal variation is studied. It is shown that in most cases, analysis of the solution makes it possible to reveal the presence of such distortions and qualitatively assess their character. It is also shown that for profile options supposedly closest to the experimental profile, the estimates have minimal bias. For all profiles, the ratio of the average and maximum errors in calculating the resistivity in different layers to the residual in the solution to the inverse problem was evaluated. This makes it possible to evaluate the actual error of the reconstructed resistivity values knowing only the fitting residual. The paper also studied the possible effect of increasing the accuracy in solving the inverse problem in the case of preliminary decomposition of the apparent resistivity curves into seasonal and flicker noise components. It is shown that for small fitting residuals, the results change insignificantly. According to the results obtained, the error in reconstructing the aperiodic (flicker noise) component of resistivity variations in the lower layers of the considered section can be decreased to 0.4%. The accuracy in reconstructing the seasonal component of resistivity variations depends on the amplitude and phase of seasonal effects in the model profile. For the considered profiles, the error varies from 1 to 2%. [ABSTRACT FROM AUTHOR]

A new technique to reduce flicker noise generated in light-fidelity (Li-Fi) transmission links based on the white light-emitting diode (LED) is proposed. Here, flicker noise with a frequency of 120 Hz, which is twice the frequency of AC power (60 Hz), is generated. The proposed technique is implemented in the receiver of the Li-Fi link. It can reduce flicker noise regardless of various digital modulation formats. In addition, there is no need to change the structure of the electrical circuit driving the LED to reduce the flicker noise. As a result, the non-return to-zero-on-off-keying (NRZ–OOK) signal waveform is tilted according to the flicker noise waveform. We implement the derivative equalization with a pseudo-flicker weight function to reduce the flicker noise. The derivative value of the NRZ–OOK signal mixed with flicker noise becomes larger than that without the flicker noise. In the proposed technique, the derivative value between adjacent sampling points is suppressed below the preset thresholds when it is greater than the preset threshold. Furthermore, a pseudo-flicker weight function is applied to accelerate the flicker noise reduction. As a result, using the proposed technique, a 2 dB signal-to-noise ratio (SNR) gain is obtained based on the bit error rate (BER) threshold (3.5 × 10−5) corresponding to 10% flicker modulation, which is known to have no serious effect on human health. This means that it is possible to implement a Li-Fi transmission link based on an illumination environment with a flicker modulation reduced from 10% to 7%. [ABSTRACT FROM AUTHOR]

We present design techniques for single-bit continuous-time delta–sigma modulators that attain high resolution (>16 bits) over a bandwidth (BW) that is more than ten times the audio range. We introduce the zapped, virtual-ground-switched dual return-to-open DAC which is immune to ISI and other transition-dependent errors. FIR feedback facilitates chopping, improves clock-jitter sensitivity and the loop filter’s linearity. We show that the compensation FIR DAC, which is typically bulky, can be implemented in an extremely power- and area-efficient manner in a single-bit modulator using a capacitive DAC and passive summation. Thanks to these techniques, the fabricated prototype achieves 103.2-/104.3-dB signal to noise and distortion ratio (SNDR)/signal to noise ratio (SNR) in a 250-kHz bandwidth while operating at 48 MS/s. Consuming 17.7 mW from a 1.8-V supply, the modulator occupies 1.1 mm 2 in a 180-nm CMOS process. The Schreier (SNDR) figure of merit (FoM) is 174.7 dB. [ABSTRACT FROM AUTHOR]

Signal-based acoustic emission data are analysed in this research work for identifying the damage modes in carbon fibre–reinforced plastic (CFRP) composites. The research work is divided into three parts: analysis of the shifting in the spectral density of acoustic waveforms, use of waveform entropy for selecting the best wavelet and implementation of wavelet packet transform (WPT) for identifying the damage process. The first two methodologies introduced in this research work are novel. Shifting in the spectral density is introduced in analogous to 'flicker noise' which is popular in the field of waveform processing. The entropy-based wavelet selection is refined by using quadratic Renyi's entropy and comparing the spectral energy of the dominating frequency band of the acoustic waveforms. Based on the method, 'dmey' wavelet is selected for analysing the waveforms using WPT. The slope values of the shifting in spectral density coincide with the results obtained from WPT in characterising the damage modes. The methodologies introduced in this research work are promising. They serve the purpose of identifying the damage process effectively in the CFRP composites. [ABSTRACT FROM AUTHOR]

The analog AI core concept is appealing for deep‐learning (DL) because it combines computation and memory functions into a single device. Yet, significant challenges such as noise and weight drift will impact large‐scale analog in‐memory computing. Here, effects of flicker noise and drift on large DL systems are explored using a new flicker‐noise model with memory, which preserves temporal correlations, including a flicker noise figure of merit (FOM) Ar to quantify impacts on system performance. Flicker noise is characterized for Ge2Sb2Te5 (GST) based phase‐change memory (PCM) cells with a discovery of read‐noise asymmetry tied to shape asymmetry of mushroom cells. This experimental read polarity dependence is consistent with Pirovano's trap activation and defect annihilation model in an asymmetric GST cell. The impact of flicker noise and resistance drift of analog PCM synaptic devices on deep‐learning hardware is assessed for six large‐scale deep neural networks (DNNs) used for image classification, finding that the inference top‐1 accuracy degraded with the accumulated device flicker noise and drift as ∝Ar×twait, and ∝twait−ν, respectively, where ν is the drift coefficient. These negative impacts could be mitigated with a new hardware‐aware (HWA) (pre)‐training of the DNNs, which is applied before programming to the analog arrays. [ABSTRACT FROM AUTHOR]

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This letter presents a 2.4-GHz high-gain, low-power, and low-noise complementary metal–oxide–semiconductor (CMOS) mixer using a current-reused bleeding amplifier. To reduce flicker noise, a resonant inductor and a current bleeding circuit are conventionally adopted, which also increases the conversion gain. In this letter, the conventional current bleeding circuit is modified to a current-reused bleeding amplifier to further increase the conversion gain, which also further decreases noise while consuming the same current, compared to the conventional circuit. Measurement results show a conversion gain of 14.64 dB, a noise figure of 9.17 dB at 10 kHz and 7.23 dB at 100 MHz, and an input third-order intercept point (IIP3) of −15.89 dBm. The proposed mixer has a power consumption of 3.82 mW from a 1.5-V supply voltage. It was fabricated by using a 65-nm CMOS process. [ABSTRACT FROM AUTHOR]

Summary: Flicker noise and white noise from the charge pump (CP) within a phase locked loop (PLL) are key contributors to the close‐in phase noise floor of a fractional‐N frequency synthesizer. The pulse train from the phase frequency detector imposes different types of random pulse modulation on the up and down current sources, which causes different modulation effects to the flicker and white noises at low frequency. This paper rigorously analyzes the underlying noise random modulation mechanisms for the system operating in integer‐N and fractional‐N modes. Transient noise simulation using Verilog‐A behavioral modeling followed by power spectrum analysis is applied to support the mathematical analysis of the random noise modulation. [ABSTRACT FROM AUTHOR]

In this work, a differential ring VCO architecture and its phase noise are inspected. Resistor bridges are added between the stages that, as evident through theory and simulation, are capable of reducing flicker and thermal noise upconversion. A differential two-stage ring VCO is considered operating at 2.5 GHz for simulation in 180 nm CMOS technology which show phase noise reduction by 4 dBc/Hz and 6.5 dBc/Hz at 10 kHz offset frequency for resistor values of 11 k Ω and 5 k Ω respectively with similar power dissipation compared to the unmodified architecture. Similar reduction in phase noise also observed in a three-stage structure operating at 1.5 GHz. [ABSTRACT FROM AUTHOR]

Modern CMOS image sensors generally face difficulties in limiting the noise effect of their readout circuits. The existing noise sources range from spatial to temporal noise, such as the thermal, the flicker, and the random telegraph signal noise sources. The noise sources and the device's image quality issues become more evident when targeting design goals, such as high resolution and high frame-rate. This paper focuses on the theoretical derivation of the Correlated Multiple Sampling technique by means the Discrete Fourier Transform in which it explicitly includes the noise contamination process during the image sensor readout operation. The purpose of the proposed approach is to deepen the underlying multiple sampling process role in low noise systems and how beneficial this technique is in suppressing the noise contamination, as such proposing a more intuitive way to understand the method. [ABSTRACT FROM AUTHOR]

Large-scale simulations and analysis of the original powers of 2 geometric source sum algorithm for simulating 1 / f noise confirm that it provides a reasonably accurate approximation to an exact 1 / f spectral density with a Gaussian amplitude distribution over any arbitrarily large frequency range. This incremental algorithm is computationally efficient with a computation time, after initialization, that varies linearly with the number of samples generated. A new variation allows non-integer and random ratios for the geometric sequence that reduces variations about the exact power-law spectral density and, by varying individual source amplitudes, produces generalized 1 / f β noises. [ABSTRACT FROM AUTHOR]

The flicker noise modeling is of great significance in many applications of high electron mobility transistors (HEMTs) in low noise circuits. In this letter, a novel charge-based flicker noise model for HEMTs is proposed, which introduces the trap-charge fluctuation-based flicker noise modeling method to the charge-based MIT virtual source (MVS) HEMT model. This model is highly compatible with the MVS HEMT model. It can predict the flicker noise performance in a physically rigorous and accurate way. This model is verified by the excellent agreement between simulations and measurement results. [ABSTRACT FROM AUTHOR]

In this article, a distributed-swing-boosting and harmonic-impedance-expanding multi-core oscillator is proposed to achieve low phase noise and high figure-of-merit (FoM), simultaneously. First, a distributed-coupling multi-core topology is introduced to reduce the chip area with no mode ambiguity. Then, the distributed-swing-boosting and harmonic-impedance-expanding structure is developed to boost the gate swing and square-like waveform of $V_{\text {DS}}$. The common-mode (CM) resonances around the second harmonic and the differential-mode (DM) resonances around the third harmonic are utilized to suppress the flicker noise up-conversion and achieve harmonic shaping. Meanwhile, the dual-resonance response expands the high-impedance frequency ranges around the harmonics, and thus, the effect of harmonic shaping can be obtained over a wide frequency range. Fabricated in a 40-nm CMOS process, the oscillator measured exhibits low phase noise and high FoM simultaneously with a compact chip size. The minimum phase noise is −138.9 dBc/Hz at the 1-MHz offset, corresponding to an FoM of 195.1 dBc/Hz. The 1/ $f^{3}$ phase noise corner is 100–130 kHz over the 26.6% tuning range. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive study of phase noise (PN) suppression in LC‐tank oscillators. The goal of this study is to provide designers with the latest techniques for reducing PN in cross‐coupled oscillators. To this end, we begin with a discussion of two prevalent PN models in oscillators: Hajimiri and Demir. We prefer the Hajimiri model because it does not involve very complicated math, and it offers engineers better insight into designing low‐PN oscillators in the two‐PN close‐in regions in an oscillator spectrum (1/f2 and 1/f3). In 1/f2 region, we show that a need for a large output‐voltage swing leads to Class D and B oscillators, and a large output‐current swing results in Class C oscillators. Also, reduction of the impulse sensitivity functions (ISFs) of an oscillator core can happen in Class F oscillators. A few solutions are presented for mitigating flicker noise up‐conversion, such as adding resistances, controlling the oscillation amplitude, decreasing the conduction angle, guiding the high‐frequency harmonics of current, and shifting the phase of VGS against VDS. We also provide a comparison of recent state‐of‐the‐art literature to show what constitutes a good PN in both 1/f2 and 1/f3 regions in cross‐coupled oscillators. We conclude that a cross‐coupled oscillator can reach the best performances in 1/f3 and 1/f2 PN regions if the oscillator is designed in Class C with the K block and uses the techniques of narrowing the conduction angle, the tail inductor, and the modified tank simultaneously. [ABSTRACT FROM AUTHOR]

Methodological studies of spectral characteristics and statistical analysis of flicker noise are presented on the example of two data samples (2016–2017) on the X-ray nova A0620-00. The results obtained indicate the nature of flicker noise as aperiodic phenomenon in stellar atmospheres and in regions of interaction between stars in binary systems, including phenomena of a flare nature. We showed that flicker noise is described by distributions of non-negative random variables: gamma distribution and Weibull distribution, which makes it related to atmospheric processes in meteorology and geological processes (earthquakes). Modeling of these processes shows structural correspondence to real data (Hurst diagrams), and also indicates the presence of additional unaccounted for noise of a presumably Gaussian nature. The performed studies give recommendations to supplement the models of the light curves of binary astrophysical systems with the gamma distribution and the Weibull distribution. [ABSTRACT FROM AUTHOR]

This article discusses the absence of methods for measuring low-frequency (LF) fluctuation processes at high temperatures and proposes an original bridge method for measuring the spectra of LF current fluctuations in the tungsten filaments of electric lamps in the controlled temperature range 300–2700 K. The application of the bridge measurement circuit reduces the influence of degradation processes in the filament and the power source's own noise on the measurement results by several orders of magnitude. A spectral analysis of LF current fluctuations is performed in the frequency range 1.5·10–5–5·10–1 Hz using an automated unit based on a personal computer under the control of specially developed software. [ABSTRACT FROM AUTHOR]

Analytical models of low-frequency noise (LFN) characteristics for planar-type tunnel field-effect-transistors (TFETs) are proposed. A surface-potential-based current–voltage model is developed to physically represent the current fluctuation due to charge trapping/detrapping in the gate dielectric. An LFN model can be analytically derived from the current fluctuation with a reasonable approximation. The proposed model is verified using Technology Computer Aided Design (TCAD) and measurement data, which are in good agreement with each other. The analytical model can not only serve as a valuable reference and tool for low-power analog circuit design but also provide physical insights into the LFN of TFETs. [ABSTRACT FROM AUTHOR]

Low-frequency noise is a critical characteristic of transistors, but there are only a few experimental works on the noise in printed electronics. In this work, we characterize the low-frequency noise of inkjet-printed electrolyte-gated thin-film transistors (EGTs) with indium-oxide semiconductors. We confirm that the carrier number fluctuation with correlated mobility fluctuation is the dominating noise generation mechanism. Also, we present the benchmark analysis on the noise level of various thin-film technologies. Notably, the extracted value of trap density near the insulator-channel interface is high, indicating an inferior quality of solution-processed and inkjet-printed thin-films. However, because of electrolyte-gating, the large areal gate capacitance compensates the negative effect of the high trap density, effectively reducing the flat-band voltage noise. As a result, the normalized drain current noise is considerably lower than solution-processed transistors and comparable with sputtered inorganic transistors with dielectric gating. This renders the electrolyte-gating approach useful in reducing the noise for printed/solution-based transistors, suitable for low-noise applications. [ABSTRACT FROM AUTHOR]

We report the 1/f noise characteristics at low frequency in graphene field-effect transistors that utilized a high-κ dielectric tantalum oxide encapsulated layer (a few nanometer thick) placed by atomic layer deposition on Si3N4. A low noise level of ∼2.2 × 10–10 Hz–1 has been obtained at f = 10 Hz. The origin and physical mechanism of the noise can be interpreted by the McWhorter context, where fluctuations in the carrier number contribute dominantly to the low-frequency noise. Optimizing fabrication processes reduced the number of charged impurities in the graphene field-effect transistors. The study has provided insights into the underlying physical mechanisms of the noise at low frequency for reducing the noise in graphene-based devices. [ABSTRACT FROM AUTHOR]

With the goal of creating single‐molecule devices and integrating them into circuits, the emergence of single‐molecule electronics provides various techniques for the fabrication of single‐molecule junctions and the investigation of charge transport through such junctions. Among the techniques for characterization of charge transport through molecular junctions, electronic noise characterization is an effective strategy with which issues from molecule–electrode interfaces, mechanisms of charge transport, and changes in junction configurations are studied. Electronic noise analysis in single‐molecule junctions can be used to identify molecular conformations and even monitor reaction kinetics. This review summarizes the various types of electronic noise that have been characterized during single‐molecule electrical detection, including the functions of random telegraph signal (RTS) noise, flicker noise, shot noise, and their corresponding applications, which provide some guidelines for the future application of these techniques to problems of charge transport through single‐molecule junctions. [ABSTRACT FROM AUTHOR]

This communication presents the performance analysis and impact of low frequency flicker noise on a dual dielectric pocket heterojunction silicon on insulator (SOI) tunnel FET (TFET). The proposed TFET structure is well optimized for different gate-source underlap length and various thickness of δp+ Si1-xGex layer. It offers an ON current of 1.16 × 10−4 A/μm providing a high ON/OFF ratio of 3.49 × 1012 and a super steeper sub-threshold swing of 2 mV/dec. The device performance is investigated with concern to interface traps while both Uniform and Gaussian trap distributions are considered. The analyses specify that the proposed device is insusceptible to ON current degradation in presence of interface traps in comparison to OFF current behaviour. Electrical noise performance is examined in presence of interface traps and different mole fraction of germanium (Ge) in δp+ Si1-xGex layer. The device is further tested for its parasitic capacitances and transconductance to drain current ratio (gm/ID) behaviour. The high ratio of obtained gm/ID makes it compatible for future low power applications. [ABSTRACT FROM AUTHOR]

This paper presents a down-conversion active mixer with improved performance for direct conversion receivers in wireless local area networks. The effect of negative admittance on the Gilbert cell mixer performance is investigated in terms of flicker noise, conversion gain, and linearity. The proposed negative admittance is implemented using a modified negative capacitance connected in parallel to a negative resistance, which exhibits a high degree of freedom to achieve high negative capacitance along with low negative resistance. The proposed mixer is designed and simulated using TSMC 0.18 µm CMOS technology in Cadence Spectre-RF at the input frequency of 2.4 GHz and intermediate frequency of 10 MHz. Post-layout simulation results show using the negative admittance can improve the flicker noise more than 16.7 dB at the frequency of 1 kHz. The proposed mixer exhibits a conversion gain of 19.3 dB and a flicker noise corner frequency of 5 kHz. The double-side band noise figure is 7.57 dB at the output frequency of 10 MHz, and the third-order intermodulation intercept point (IIP3) is − 7.5 dBm. The power dissipation is 13.6 mW from the power supply of 1.8 V. Moreover, the linearity of the proposed mixer can be enhanced by choosing the proper values for transconductance of switching quad and negative resistance so that it achieves the IIP3 of + 7.9 dBm with the conversion gain of 7.6 dB. [ABSTRACT FROM AUTHOR]

This article presents a comparative low-frequency noise (LFN) characterization of gate-all-around nanosheet n-channel Si metal–oxide–semiconductor field effect transistors, processed with three different metal gates (MGs): an aluminum-based reference process and two alternative effective work function (EWF) stacks. In all cases, the gate dielectric is composed of HfO2 over an SiO2 interfacial layer. The LFN figures of merit are extracted, such as the oxide trap density and Coulomb scattering coefficient, and the correlations with the threshold voltage and the electron mobility are investigated. Carrier number fluctuations are confirmed as the dominant mechanism of the 1/ƒ noise for all evaluated devices. Additionally, it is shown that the specific MG can contribute to the carrier scattering, degrading the electron mobility. The most promising results are obtained for one of the alternative MGs, exhibiting a low oxide trap density level, a low threshold voltage and insignificant mobility degradation. [ABSTRACT FROM AUTHOR]

Noise Reduction with less computational time and resources of the signal is a major requirement in signal processing. In the real-world scenario, Electromyography (EMG) signals often affect by various noises. The EMG signal requires noise reduction to obtain an accurate diagnosis process. In this study, Ladner-Fischer Adder (LFA) based Median Filter (MF) architecture is used to remove the noise from the EMG signal. The noise evaluation process is included in this proposed method to eliminate the flicker noise from the signal. The proposed LFA-MF method is simulated in the Cadence RTL compiler and Xilinx tool to evaluate the performance in terms of power, delay and Look Up Table (LUT). The objective of this work is to design the noise detection structure to avoid the denoising process for all the samples. This helps to reduce the hardware resources of the entire median filter architecture. The simulation result of LFA-MF architecture showed that it has lower power consumption and delay in noise reduction. The LFAMF architecture has a power consumption of 1006548 nW in 16-bit sample width, while the existing method has 1537940 nW power consumption. [ABSTRACT FROM AUTHOR]

This study presents a new low-power and low-phase noise Colpitts quadrature voltage-controlled oscillator (QVCO). The proposed QVCO contains two differential Colpitts voltage-controlled oscillators (VCOs) that use gain-boosting technique to enhance the negative transconductance and relax start-up condition. Both switching and tail transistors are configured in class-C to improve impulse sensitivity function and phase noise performance of the circuit via better noise modulation function. In addition, flicker noise would be reduced because of the switched-biasing mechanism of tail transistors. Phase noise analysis shows that changing the bias voltage of switching as well as tail transistors can improve the phase noise performance of the core VCO with overlap reduction of the transistors active time. Consequently, due to no extra noisy elements for coupling and class-C biasing of all transistors, low-phase noise quadrature signals are generated. To verify the performance of the proposed technique, post-layout simulation is performed in Taiwan Semiconductor Manufacturing Company (TSMC) of 0.18 μm Radio Frequency-Complementary Metal-Oxide- Semiconductor (RF-CMOS) process at a supply voltage of 1.2 V. Post-layout simulation results show that the phase noise of the proposed QVCO is −120.6 dBc/Hz at 1 MHz offset from 5.73 GHz operation frequency. The total power consumption of the QVCO is 3.1 mW and the tuning range is from 5 to 5.73 GHz. [ABSTRACT FROM AUTHOR]

This study presents a new low‐power and low‐phase noise Colpitts quadrature voltage‐controlled oscillator (QVCO). The proposed QVCO contains two differential Colpitts voltage‐controlled oscillators (VCOs) that use gain‐boosting technique to enhance the negative transconductance and relax start‐up condition. Both switching and tail transistors are configured in class‐C to improve impulse sensitivity function and phase noise performance of the circuit via better noise modulation function. In addition, flicker noise would be reduced because of the switched‐biasing mechanism of tail transistors. Phase noise analysis shows that changing the bias voltage of switching as well as tail transistors can improve the phase noise performance of the core VCO with overlap reduction of the transistors active time. Consequently, due to no extra noisy elements for coupling and class‐C biasing of all transistors, low‐phase noise quadrature signals are generated. To verify the performance of the proposed technique, post‐layout simulation is performed in Taiwan Semiconductor Manufacturing Company (TSMC) of 0.18 μm Radio Frequency‐Complementary Metal‐Oxide‐ Semiconductor (RF‐CMOS) process at a supply voltage of 1.2 V. Post‐layout simulation results show that the phase noise of the proposed QVCO is −120.6 dBc/Hz at 1 MHz offset from 5.73 GHz operation frequency. The total power consumption of the QVCO is 3.1 mW and the tuning range is from 5 to 5.73 GHz. [ABSTRACT FROM AUTHOR]

This article shows how to properly define modulated flicker noise in Verilog-A compact models, and how a simulator should handle flicker noise for periodic and transient analyses. By considering flicker noise in a simple linear resistor driven by a sinusoidal source, we demonstrate that the absolute value formulation used in most existing Verilog-A flicker noise models is incorrect when the bias applied to the resistor changes sign. Our new method for definition overcomes this problem, in the resistor as well as more sophisticated devices. The generalization of our approach should be adopted for flicker noise, replacing the formulation in existing Verilog-A device models, and it should be used in all new models. Since Verilog-A is the de facto standard language for compact modeling, it is critical that model developers use the correct formulation. [ABSTRACT FROM AUTHOR]

We present design considerations for CTΔΣMs that attempt to achieve high resolution (16+ bits) over a wide bandwidth (>200 kHz), resulting in a low in-band noise spectral density. The main challenges in such designs are parasitic resistance in the reference path, inter-symbol interference (ISI) in the feedback-digital-to-analog converter (DAC) waveform, and flicker noise of the input operational transconductance amplifier (OTA). We introduce the virtual-ground-switched resistor DAC as a way to achieve low distortion by addressing parasitic resistance in the reference path and reducing the effects of ISI. Flicker noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a three-stage OTA and finite impulse response (FIR) feedback. These techniques are applied to the design of a 250 kHz bandwidth CTΔΣM targeting 108 dB signal-to-noise-and-distortion-ratio (SNDR) in a 180 nm CMOS process. The fabricated prototype, which operates at 32 MS/s, achieves 105.3/108.1 dB SNDR/signal-to-noise-ratio (SNR) and consumes 24 mW. The Schreier SNDR figure of merit (FoM) is 175.5 dB. [ABSTRACT FROM AUTHOR]

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Silicon–carbon (SiC) strained nMOSFETs with sub-35-nm gate length in a 40-nm CMOS technology can realize superior cutoff frequency ($f_{T}$) up to 405 GHz, attributed to more than 20% enhancement of the mobility and transconductance. This super-400-GHz $f_{T}$ makes SiC strained nMOS an attractive high mobility device aimed at millimeter-wave (mm-wave) CMOS circuits design. However, the SiC nMOSFETs reveal a dramatic increase in flicker noise and random telegraph noise (RTN), which may cause worse phase noise and detrimental impact on CMOS oscillator stability. The complex RTN features abnormally long capture and emission time constants ($\tau _{c}$ and $\tau _{e}$) and suggests electron-phonon coupling responsible for the anomalously slow trapping and detrapping, due to a significant increase of relaxation energy from SiC strain. This critical tradeoff between high-frequency performance and low-frequency noise becomes a key factor to be considered for the most appropriate adoption of high mobility devices and design optimization adapted to various circuits. [ABSTRACT FROM AUTHOR]

Summary This paper analyzes the thermally induced phase noise and the up‐conversion of flicker noise into phase noise of source injection coupled quadrature oscillator (SIC‐QOSC), for the first time. Furthermore, this paper provides a complete analysis for the injection current of the SIC‐QOSC and extracts the closed‐form expressions for it for the first time, too. These expressions lead to obtaining the harmonics of the injection current as well as the oscillation amplitude, which is necessary for the phase noise analysis. To evaluate the extracted equations, this paper compares the calculated results with appropriate simulations. Comparisons confirm the accuracy of the proposed injection current expressions and the phase noise formulas. Using the closed‐form equations of phase noise, designers can understand the SIC‐QOSC's design tradeoffs and design the oscillator for given phase noise. [ABSTRACT FROM AUTHOR]

In this paper, a novel circuit method is proposed to reduce 1/f3 (close-in) phase noise in a cross-coupled LC Voltage Control Oscillator (VCO) by suppressing flicker noise power of the tail transistor. Using an added resistor between drain and gate of the tail transistor, that works as a negative feedback, the tail transistor flicker noise is suppressed, and therefore, the 1/f3 output phase noise is reduced by 5.7 dB. Also, the added resistor helps in better tail current shaping for phase noise reduction. The proposed oscillator is designed in a 0.18 μ m CMOS technology with 1.8 V supply and 3.6 mW power consumption. Post-layout simulations predict a phase noise of − 1 0 4 dBc/Hz for the proposed oscillator at 100 KHz offset from 3.1 GHz carrier frequency. Mathematical analysis is included in the paper for confirmation of the phase noise performance enhancement. The Figure of Merit (FOM) of the proposed oscillator is 188.3 and 190.6 dBc/Hz at 100 KHz and 1 MHz offsets, respectively. [ABSTRACT FROM AUTHOR]

This manuscript presents a systematic low–frequency noise analysis of inversion–mode vertically stacked silicon n–channel nanosheet MOSFETs on bulk wafers. Flicker noise due to carrier number fluctuations is shown as the dominant noise source, which is in line with previous reported studies on gate-all-around (GAA) nanowire nMOSFETs. In addition, the benchmark points out that the vertical stacking approach does not deteriorate the oxide trap density, since its normalized input–referred voltage noise Power Spectral Density at flat–band is lower compared to the data on non–stacked horizontal nanowire nMOSFETs. Another finding is that the Coulomb scattering mechanism dominates the mobility. [ABSTRACT FROM AUTHOR]