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The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation. [ABSTRACT FROM AUTHOR]

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures. [ABSTRACT FROM AUTHOR]

Unprecedented growth in CMOS technology and demand of high-density integrated circuits (ICs) in semiconductor industry has motivated to research community towards the development of MOS technology from micrometre regime to nano-meter regime. This paper presents the development of MOS technology from classical MOS technology to non-classical MOS technology and their extensions of learning towards the machine. Firstly, the studies are analysed with the scaling and limitations of bulk MOSFET beyond 100 nm in terms of constant and voltage field scaling and various short channel effects. Then we investigated the non-classical device architecture beyond 32 nm such as multiple-gate field-effect transistors, SOI MOSFETS, FINFETs, and gate-all-around FETs for the replacement of traditional CMOS devices. Next, we discussed the different architectures in the sub nano-technology regime. These structures include Carbon Nano Transistors, Single Electron Transistors (SET), Graphene Nano Ribbon, Nano Wire, and Nano Sheet Transistors. It is very conceivable that these kinds of devices will be utilized in the construction of high-density integrated electronic computers in near future. Lastly, we extend our studies on different machine learning method like ANN, KNN, DNN and Random Forest for the optimization of MOSFET, SOI FET, TFET, FinFET and GAA FET. [ABSTRACT FROM AUTHOR]

A trajectory comparison method is proposed to study the impact of back-gate radiation on single-event effects (SEE) of ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) MOSFETs using Synopsys Sentaurus technology computer-aided design (TCAD) tools. Based on the series coupling capacitance model of the threshold voltage, the influence of device parameters such as buried oxide (BOX) thickness, ground plane doping and back biasing on the back-gate radiation effect is analyzed. The electrostatic potential difference between the BOX/substrate interface and substrate region decreases due to the reduced width of the substrate depletion region caused by back-gate radiation, leading to a positive shift in the threshold voltage and a decrease in the transient leakage current. The back-gate radiation effect is enhanced with reduced BOX layer thickness and ground-plane doping. UTBB FDSOI devices under reverse back biasing from 0 V to −0.5 V, which expands the depletion region, show a more dramatic decrease in the transient leakage current than those under forward back biasing. The findings contribute to a better understanding of the SEE mechanism of UTBB FDSOI devices and are helpful in radiation hardness optimization. [ABSTRACT FROM AUTHOR]

This paper presents an experimental study on the high-dose-rate transient ionizing radiation response and influencing factors of a Nano-Scale Fully Depleted Silicon-On-Insulator (FDSOI) D flip-flops (DFFs) circuit. Results indicate that data errors occur in DFFs at the lowest dose rate of 4.70 × 1011 rad(Si)/s in experiments, and the number of data errors shows a nonlinear increasing trend with the increase in dose rate and supply voltage. Three-dimensional technology computer-aided design (TCAD) simulations were conducted to analyze the transient photocurrent and charge collection mechanism at advanced process. The simulation results indicated that the charge collection efficiency is heightened with an increase in supply voltage, resulting in the higher photocurrent. This plays a major role in the process of charge collection for Ultra-Thin Body and Buried oxide (UTBB) FDSOI technology. The investigation into the high-dose-rate transient ionizing radiation effect (HDR-TIRE) in Nano-Scale FDSOI DFFs will aid in the assessment and application of advanced integrated circuits in aerospace. [ABSTRACT FROM AUTHOR]

A leap towards deriving a robust-compact model for ferroelectric-FET (FeFET) oscillator based spiking neurons has been developed. The compact model can capture and emulate neurons that exhibit both excitatory and inhibitory coupled dynamical behaviour, native to cortical neurons. The proposed model can reliably mimic neuronal dynamics for a broad-spectrum of FeFETs when, factored with appropriate validation of numerical simulations and physics-based models. The emulation of neuronal attributes based on FDSOI FeFET having qualitative agreement with previously reported data. The robustness of this analytical model has been investigated by tuning with ferro-dielectric (Fe) materials i.e., zirconium-doped HfO2 (HZO) and silicon-doped HfO2 (HSO) for mimicking the neurons. In continuance, the model is examined for emulating the cortical neurons by altering the inhibition (high-VGF) and excitation (low-VGF) inputs with a suitable frequency of operation for spiking neurons. [ABSTRACT FROM AUTHOR]

Recent years have seen an increasing popularity in the development of brain-inspired neuromorphic hardware for neural computing systems. However, implementing very large scale simulations of neural networks in hardware is still an open challenge in terms of power efficiency, compactness, and biophysical resemblance. In an effort to design biologically plausible spiking neuron circuits while restricting power consumption, we propose a new subthreshold Leaky Integrate-and-Fire (LIF) neuron circuit designed using 22 nm FDSOI technology. In this circuit, problems of large leakage currents and device mismatch are effectively reduced by deploying the back-gate terminal of FDSOI technology for a tunable design. The proposed neuron is able to operate in two spiking frequency modes with tunable bias parameter setting of key transistors, and it results in complex firing behaviors, such as adaptation, chattering, and bursting, through varying bias voltages. We present circuit post-layout simulation results and demonstrate the biologically plausible neural dynamics. Compared with published state-of-the-art neuron circuits, the circuit dissipates ultra-low energy per spike, on the order of femtojoules per spike, at firing rates ranging from 30 Hz to 1 kHz. Furthermore, the circuit is proven to maintain a good robustness over process variation and Monte Carlo analysis, with relative error 3.02% at a firing rate of approximately 67.1 Hz. [ABSTRACT FROM AUTHOR]

In this article, negative capacitance effect on metal-ferro-metal-insulator-semiconductor (MFMIS) type FDSOI negative-capacitance-FET (NCFET) has been investigated by considering two well known thin-film ferro-dielectric ($ Fe$) materials HZO (zirconium:HfO $_{2}$) and HSO (silicon:HfO $_{2}$). The investigations are carried out in a well calibrated TCAD environment, where the gate-charge ($ Q_{G}$) is extracted from the TCAD simulation. And, subsequently computing the ferro-voltage ($ V_{Fe}$) across $ Fe$ -capacitor to estimate the total effective gate voltage ($ V_{GS}$) on the gate-stack of FDSOI NCFET. The depicted values are subjected to increment in $ Fe$ -thickness ($ t_{Fe}$) to optimize HZO and HSO $ Fe$ -materials for FDSOI NCFET(s). The optimised NCFET(s) are later levied with back-gate bias (V $_{\mathrm{B}}$) variation with the motivation of utilizing the attributes of FDSOI MOSFETs of V $_{\text{TH}}$ shift can further enhance the device performance. Depicted results has shown the HZO- $ Fe$ offers superior improvement in sub-threshold slope (SS), peak-transconductance (g $ _{m}$) and off-current (I $_{\text{OFF}}$) at lower $ t_{Fe}$ with the expense of lower endurance to hysteresis. On the other hand, the HSO- $ Fe$ predicts improvement in SS, peak-g $ _{m}$ and I $_{\text{OFF}}$ with higher endurance towards hysteresis in-spite of $ t_{Fe}$ thickness under sub-10 nm regime. Similarly, the V $_{\mathrm{B}}$ variation have shown similar results where the HSO NCFET has predicted slightly higher enhancement in performance aspect than HZO NCFET owing to the V $_{\text{TH}}$ shift phenomena attributed to FDSOI architecture and HSO- $ Fe$ comprehensible polarization duality. [ABSTRACT FROM AUTHOR]

FDSOI (Fully Depleted Silicon On Insulator) devices have a good performance in anti-single-event circuits. However, the bipolar amplification effect becomes a severe problem due to the buried oxide. The previous models for Single Event Transient (SET) of FDSOI did not fully consider the current of all components. Most importantly, they did not take the influence of the back-gate voltage into account. Thus, this paper presents a modeling method for the SET current in FDSOI MOSFET where all three components are modeled individually. The prompt current and diffusion current are modeled with a current source respectively. The Berkeley Short-channel IGFET Model for Silicon-on-Insulator (BSIMSOI) model is integrated into this model to calculate the bipolar amplification current. Compared to using the bipolar transistor model, this method avoids additional current input from the base electrode. It is more consistent with the mechanism of bipolar amplification effect for FDSOI devices without body contact. Instantaneously, an improved model is proposed that considers the influence of the back-gate voltage on the SET of the FDSOI devices. All models are validated through Technology Computer Aided Design (TCAD)simulation results. [ABSTRACT FROM AUTHOR]

The performance of the ultra-thin body and buried oxide fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistors based on a 22 nm technology node is investigated in this paper over an ultra-wide temperature range from 6 K to 550 K. The currentâ€"voltage (I â€" V) characteristics under wide temperature range conditions are shown, including the influence of the back-gate bias (V bg). The important electrical parameters, such as threshold voltage (V t), subthreshold swing, ON-state current (I on), and OFF-state current (I off), are extracted with temperature changes. From 550 K to 6 K, V t increased by 0.21 V, I off decreased nearly six orders of magnitude, and the gate-induced drain leakage current decreased by nearly eight orders of magnitude. The main physical mechanisms for the changing electrical performance with temperature are the variation of carrier concentration, mobility, and energy band. By utilizing a technology computer-aided design simulation, the temperature dependence of the device performance is discussed and analyzed. [ABSTRACT FROM AUTHOR]

Herein, a method for the electrical characterization of a fully depleted silicon‐on‐insulator (FDSOI) high‐k dielectric‐metal‐gate stack is proposed. The method is based on assessing low‐field mobility in FDSOI field‐effect transistor (FET) from current–voltage measurements at various temperatures in the gate voltage range up to strong inversion. In addition to assessing the value of the low‐field mobility for the stack itself, it allows specifying the impact of various carrier‐scattering mechanisms on the total stack mobility. Further, the application of double‐gate operation in the optimal coupling mode for the FET allows analysis of the impact of the gate interfaces on mobility. The method can be used in the monitoring of stack quality and in the design and development of stack fabrication processes. [ABSTRACT FROM AUTHOR]

In this paper, the self-heating effect for multi-finger fully depleted SOI nMOSFETs is investigated. The layout parameters of the transistor are varied, and the conductance-based method is used for the extraction of the thermal resistance. An empirical-based scalable thermal resistance model that accounts for geometrical layout parameters is developed. Further, hot carrier stress degradation is examined, and a correlation between self-heating and hot carrier degradation is established. The associated self-heating with geometrical dimension influences the amount of hot carrier degradation and should be taken into account for accurate degradation modeling. It is found that with the increase of temperature, the contribution of the parasitic bias temperature instability effect increases the drift of the threshold voltage. Improved thermal and reliability performance is achieved for the device structures where a continuous active area is divided into multiple smaller active regions. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistor (FeFET)-based circuit implementation mimicking FitzHugh-Nagumo neuron is proposed in this work. The proposed circuit is shown to mimic biological neuron properties, such as excitation block and anodal break excitation which are not mimicked by an integrate and fire neuron model. We also show a winner-take-all circuit that can be used with this proposed neuron implementation. The neuron implementation requires just one FeFET, three baseline field-effect transistors, and one capacitor, making it area and energy-efficient. The neuron circuit, with minimum sized transistors, consumes approximately 10 pJ per spike. The neuron’s energy consumption per spike can be reduced to as low as 100 fJ by designing some of the transistors with aspect ratio less than one. [ABSTRACT FROM AUTHOR]

The flexibility of field-programmable gate arrays (FPGAs) is attributed to the reconfigurability of their basic logic elements (BLEs). Traditionally, the BLEs are comprised of one or more lookup tables (LUTs) of $n$ inputs, that are designed to implement Boolean functions of $n$ or fewer inputs. In an attempt to reduce the area and power consumption that comes from using LUTs, a number of complex LUT architectures have been reported. Although most of the proposed complex LUT architectures have resulted in reduced area and power, this has always been at cost of the decreased performance. This article proposes a new FPGA architecture, called threshold logic FPGA (TLFPGA), which results in significant improvement in performance, power, and area (PPA). TLFPGA is comprised of a combination of LUTs and a new type of BLE referred to as a threshold logic cell (TLC) (Muroga, 1987). Although TLCs implement a relatively small subset of Boolean functions known as threshold functions (Muroga, 1987), they require far fewer registers and multiplexers than an LUT, and are also significantly faster. This article describes the architecture of the TLFPGA and a technology mapping algorithm tailored for a TLFGA. On average, TLFPGA designs use 18% fewer registers and multiplexers, which improves the collective area of BLEs by approximately 16%, power by 14%, and performance by 5%. The improvements have been demonstrated in both 40 and 28 nm technologies for ISCAS-85 circuits as well as practical circuits, using industry-standard flows. The improvements were also demonstrated using a layout of the architecture. [ABSTRACT FROM AUTHOR]

A frequency-reconfigurable SP4T switch is presented, in which ${R}_{\text {ON}} \times {C}_{\text {OFF}}$ characteristics of switch transistors are enhanced with plaid metal transistors and forward body biasing. Plaid metal transistors (PMT) with forward body bias (FBB) are used for all of the transistors to enhance the FoM. The plaid patterned metal accesses of a transistor for the source and drain decrease the extrinsic resistance and capacitance. FBB increases the overdrive voltage of a transistor and decreases the on-resistance. The SP4T switch includes main switch matrices that route an input signal to four-outputs, a switched inductor (SI) network, and a mode-selection switch. The SI network connected through the mode-selection switch resonates out the off-capacitances of the main switch matrices at RF in the RF mode. The SP4T switch operates without the SI network in DC mode. The SP4T switch is implemented in a 28-nm FDSOI CMOS process. The core area occupies 0.2 mm2. The switch shows less than 2 dB insertion loss from DC to 4.4 GHz in the DC mode and from 4.4 to 5.3 GHz in the RF mode, where isolations are more than 16.8 dB and 18 dB, respectively. [ABSTRACT FROM AUTHOR]

Industrial plants suffer from a high degree of complexity and incompatibility in their communication infrastructure, caused by a wild mix of proprietary technologies. This prevents transformation toward Industry 4.0 and the Industrial Internet of Things. Open platform communications unified architecture (OPC UA) is a standardized protocol that addresses these problems with uniform and semantic communication across all levels of the hierarchy. However, its adoption in embedded field devices, such as sensors and actuators, is still lacking due to prohibitive memory and power requirements of software implementations. We have developed a dedicated hardware engine that offloads processing of the OPC UA protocol and enables the realization of compact and low-power field devices with OPC UA support. As part of a proof-of-concept embedded system, we have implemented this engine in a 22-nm FDSOI technology, representing the first ASIC implementation of an OPC UA server. We measured performance, power consumption, and memory footprint of our test chip and compared it with a software implementation based on open62541 and a Raspberry Pi 2B. Our OPC UA hardware engine is 50 times more energy efficient and only requires 36 KiB of memory. The complete system consumes only 24 mW under full load, making it suitable for low-power embedded applications. [ABSTRACT FROM AUTHOR]

In this work, we assess the applicability of the well-known split CV technique for mobility extraction in 28 nm FDSOI transistors with gate length down to 25 nm using TCAD simulations. We identify the significant bias dependence of the parasitic source/drain resistance and the contribution of the inner fringing capacitance as the main sources of error in the conventional split CV extraction. An improved split CV method, correcting for these parasitics, is demonstrated to accurately extract the effective mobility and its dependence on the gate voltage for devices down to 25 nm gate length. Measurements on 28 FDSOI transistors confirm the insights from the TCAD simulations. [ABSTRACT FROM AUTHOR]

A triple modular redundancy SRAM was designed as the embedded high-speed memory for a radiation-tolerant ARM processor with ST Microelectronics 28-nm FDSOI technology. The single event upset (SEU) cross-section of the SRAM was tested by using heavy ions with the linear energy transfer of 15.0 meV.cm2.mg−1 in both non-TMR and TMR modes with different accumulated fluence. The SRAM cell was also simulated by using Cogenda TCAD simulation suite and the cross section was calculated by using analytic method. The results showed the cross-section is around 2E-10 cm2/bit in non-TMR mode, and in TMR mode it varied from one to several orders lower than the non-TMR mode according to the specific accumulated fluence. As a scrubbing circuit was designed to reduce the accumulated number of SEUs in the SRAM, the Failure In Time (FIT) rate at sea level in New York City could be as low as 8E-11, which is robust enough for the whole circuit. [ABSTRACT FROM AUTHOR]

This brief presents the design of an ultra-low-power frequency synthesizer based on a feedback loop composed of an improved version of the Factorial Delay-Locked Loop (F-DLL). Its output frequency is controlled by a set of current-starved delay units tuned by a standard DLL feedback loop and a set of logic circuits to generate an RF output frequency proportional to the reference. The objective of this circuit is to achieve a power consumption in the micro-watt range to generate the desired output frequency proportional to the reference frequency between 1.5 and 2.0 GHz, being capable of supporting a wide range of input frequencies with a low phase noise (lower than −90 dBc/Hz at 1 MHz offset) and $370~\mu \text{W}$ of power consumption. In order to ensure the locking state of the feedback loop and to reduce the phase noise, a modification of the biasing circuit for the voltage-controlled delay line (VCDL) is used to improve the linearity of the frequency response of the output using a complementary feedback loop architecture. The circuit was designed and fabricated using the 28 nm FDSOI technology from STMicroelectronics and the measurement results are presented. [ABSTRACT FROM AUTHOR]

In this paper, a twin-FET (field effect transistor) THz detector monolithically integrated with a dual-feed antenna is presented. The antenna-detector configuration can be extended for ’N’ FET elements to relax the input impedance requirement for the detector readout circuitry while maintaining good responsivity. A dual-feed octagonal slot antenna is used to couple THz radiation and provide differential excitation to the twin-FET detector. The multi-feed antenna-FET detector interface can be designed for an arbitrary phase excitation of one or more FET elements. Fabricated in Global Foundries 22nm FD-SOI process, the proposed detector covers a measured frequency range from 220 GHz to 300 GHz. Such bandwidth is sufficiently wide to capture reliable spectral information for distinguishing a number of gases in a mixture. The absorption spectra of pure methanol, chloromethane and acetonitrile are measured using a rotational spectroscopy setup incorporating the twin-FET detector. Detection of a small concentration of acetonitrile, at 4 Torr pressure, is demonstrated in a binary mixture with predominantly chloromethane. Detection of ethanol and methanol in their binary mixture is also demonstrated at 4 Torr pressure. This is a significant step towards the development of all-electronic THz spectroscopy for the detection of volatile organic compounds (VOCs) in the presence of contaminants with a strong THz absorption signature at >1 Torr pressure. [ABSTRACT FROM AUTHOR]

This letter investigates the impact of read operation on the electrical properties of hafnium oxide-based ferroelectric field-effect transistors (FeFETs). We report that a quasi-static read may induce a series of phenomena, including a severe underestimation of the memory window, undesirable loss of the stored state, i.e. destructive read, increased variability and an apparent steep-slope behavior with a subthreshold slope lower than 7 mV/decade, which are not present under a fast read. We explain the results with the time-voltage dependence for the ferroelectric switching. Based on this, we provide comprehensive yet essential guidelines for disturb-free write and read operations. [ABSTRACT FROM AUTHOR]

Analog finite-impulse-response (AFIR) filtering is proposed to realize low-power channel selection filters for the Internet-of-Things receivers. High selectivity is achieved using an architecture based on only a single—time-varying—transconductance and integration capacitor. The transconductance is implemented as a digital-to-analog converter and is programmable by an on-chip memory. The AFIR operating principle is shown step by step, including its complete transfer function with aliasing. The filter bandwidth and transfer function are highly programmable through the transconductance coefficients and clock frequency. Moreover, the transconductance programmability allows an almost ideal filter response to be realized by careful analysis and compensation of the parasitic circuit impairments. The filter, manufactured in 22-nm FDSOI, has an active area of 0.09 mm 2. Its bandwidth can be accurately tuned from 0.06 to 3.4 MHz. The filter consumes 92 $\mu \text{W}$ from a 700-mV supply. This low power consumption is combined with a high selectivity: $\text{f}_{-60\,\text {dB}}/\text{f}_{-3\,\text {dB}}\,\,=$ 3.8. The filter has 31.5-dB gain and 12-nV/ $\sqrt {\text {Hz}}$ input-referred noise for a 0.43-MHz bandwidth. The OIP3 is 28 dBm, independent of the frequency offset. The output-referred 1-dB-compression point is 3.7 dBm, and the in-band gain compresses by 1 dB for an −3.7-dBm out-of-band input signal while still providing >60 dB of filtering. [ABSTRACT FROM AUTHOR]

A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasing techniques to achieve an adequate balance between the drive strength of the pull-up and pull-down networks. Measurements showed that the lowest input voltage levels, which could be upconverted by the 10 chip samples, varied from 39 mV to 52 mV. Half of the samples could upconvert from 39 mV to 1 V. The simulated energy consumption of the level shifter was 5.2 fJ for an up-conversion from 0.2 V to 1 V and 1 MHz operating frequency. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the impact of process variations on the detection of resistive short defects, in the context of a logic-based test. Two types of short defects are considered for our investigation, i.e. resistive short to either ground terminal (GND) or power supply terminal (VDD). For both defect types, simple analytical models are proposed that permit to evaluate the robust detectability range in presence of process variations. These models rely on a pre-characterization of the gate library through Monte-Carlo simulation and permit to evaluate the detectability range of a given defect without performing any fault simulation. These models are applied to perform a comparative analysis of 28 nm Bulk and FDSOI (Fully Depleted Silicon-On-Insulator) technologies, considering both regular-VT and low-VT devices. The influence of operating conditions on defect detectability range is also investigated. [ABSTRACT FROM AUTHOR]

Flexible Si nanomembrane transistors with Al2O3 and SiO2 gate dielectrics were fabricated, and their mechanical stability was compared under various bending conditions. Both the Al2O3 and SiO2 gate dielectric devices exhibited good charge transport properties, which was associated with the advantage of having a fully depleted mode in the MOSFET operation. The results of the comparison showed that the Al2O3 gate dielectric device degraded to a greater extent than the SiO2 gate dielectric device under the same bending condition. The greater degradation in the Al2O3 gate dielectric device was attributed to the higher Young’s modulus of the Al2O3, which put more strain on the Al2O3 under the same bending condition. [ABSTRACT FROM AUTHOR]

High-performance mechanically flexible Si nanomembrane (NM) fully depleted silicon-on-insulator field-effect transistors are realized via neutral mechanical plane (NMP) optimization. This NMP-optimized Si NM flexible device, using both the analytical and numerical modeling, shows excellent mechanical and electrical stability even at a bending condition with a 1 mm radius. The strain at this point is less than 0.01% that is much smaller than the strain tolerance of 0.1%. This work reveals that mechanical reliability is heavily associated with the location of the NMP and the NMP optimization is essential to realize the Si NM flexible electronics. [ABSTRACT FROM AUTHOR]

This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 \mu \textm by 250 \mu \textm . The proof-of-concept receiver was implemented in an STMicroelectronics’s 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a $4 \times 4$ subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor $\Delta \Sigma $ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator’s measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1-V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. The functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array. [ABSTRACT FROM AUTHOR]

Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are likely alternatives to traditional planar Bulk transistors for future technologies due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. However, FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit. It is therefore the objective of the paper to address this aspect. More specifically, we analyze the electrical behavior of logic gates in presence of a resistive bridging defect for these three different technologies. A particular care has been taken to design transistors and elementary gates in such a way that the comparative analysis in different technologies is meaningful. After implementing similar design in each technology, we compare the electrical behavior of the circuit with the same resistive bridging defect and we analyze both the static and dynamic impact of this defect. [ABSTRACT FROM AUTHOR]

This paper presents an in-depth analysis of the impact of body-biasing, supply voltage, and temperature on the detection of resistive short defects in FDSOI technology. Three types of short defects are considered for our investigation, namely resistive short to ground terminal, resistive short to power supply terminal (VDD), and intergate resistive bridging defect. The two implementation options offered by the technology, i.e., low VT (LVT) and regular VT (RVT) devices are also studied. Defect detectability is evaluated in the context of logic test using the concept of critical resistance. The optimal body-biasing, supply voltage, and temperature settings to achieve the maximum defect coverage are determined through HSPICE simulations using a didactic circuit implemented with 28-nm UTBB FDSOI gate library. An analytical analysis is also proposed based on the on-resistance model of P and N networks, which permits to evaluate the value of the critical resistance without performing fault simulations. In addition, this paper quantifies the individual as well as the combined improvements in detection brought by body-biasing, supply voltage, and temperature settings for the different defect types and different implementations. [ABSTRACT FROM PUBLISHER]

Achieving wireless communications at 5–30 Mb/s in energy-harvesting Internet-of-Things (IoT) applications requires energy efficiencies better than 100 pJ/b. Impulse-radio ultrawideband (UWB) communications offer an efficient way to achieve high data rate at ultralow power for short-range links. We propose a digital UWB transmitter (TX) system-on-chip (SoC) designed for ultralow voltage in 28-nm FDSOI CMOS. It features a PLL-free architecture, which exploits the duty-cycling nature of impulse radio through aggressive duty cycling within the pulse modulation time slot for high energy efficiency and minimum jitter accumulation. Wide-range on-chip adaptive forward back biasing is used for threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. To ensure spectral compliance with output power regulations without the use of bulky and expensive off-chip filters, a programmable pulse-shaping functionality is integrated in the digital power amplifier based on a 7–9-GS/s, 5-b current DAC. Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the TX alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2. [ABSTRACT FROM AUTHOR]

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors. [ABSTRACT FROM AUTHOR]

3D sequential integration is a promising alternative to conventional scaling down approach: by stacking transistors level on top of each other, benefits on device density and performance are achieved. However, although the thermal processing of top transistors is currently restricted in order to avoid bottom CMOS degradation, it has been highlighted that Ni0.80Pt0.10 silicide source/drain (S&D) contact remains the most sensitive element to the thermal budget, especially on raised Si0.7Ge0.3:B S&D for pMOS transistors. In this context, a complete and systematic study on self-aligned silicide (SALICIDE) process has been proposed: alternative metallization as well as source and drain surface pre-treatments have been carried out. Indeed, a novel Ni-based silicide, the Ni0.9Co0.1 provides a better stability on unpatterned 300 mm wafers. This stability has been further improved when combined with epitaxial silicon capping layer (Si-Cap) and Si0.7Ge0.3:B S&D preamorphization implant (PAI) using Ge beam. For the first time, a successful Ni0.9Co0.1 SALICIDE implementation has been demonstrated on pMOS planar FDSOI transistor with both PAI and Si-Cap. Moreover, the presence of Si-Cap contributes to reduce silicide roughness and limits Ge partition that damage Si0.7Ge0.3:B S&D. [ABSTRACT FROM AUTHOR]

In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are introduced in the stacked Quatro design to protect the sensitive devices of the original structure. Striking either of the stacked devices will not upset the latch because the conduction path to the supply rail is still cut off by the other off-state device. The irradiation experimental results substantiate that the stacked Quatro design has significantly better SEU tolerance (e.g., higher heavy ion upset Linear Energy Transfer threshold and smaller cross-section data) than the reference designs. It introduces power and area penalties because the proposed design duplicates and stacks two sensitive PMOS devices. Additionally, the impact of technology scaling on Quatro in various technology nodes (130-nm, 65-nm, and 40-nm) has been studied suggesting decreasing upset threshold and decreasing cross-section data. [ABSTRACT FROM AUTHOR]

In this work the variation of the FDSOI-UTTB p-MOS mobility is studied for different biases of the buried oxide. Two dielectrics are considered: HfO2 (high-k) with 8A-EOT and a SiON reference. The substrate biases (through the buried oxide) enables a mobility of about 150 cm2/V.s (90% improvement) similar to the SiON reference (with back bias) and close to the results obtained for conventional high-k n-MOS. This 90% improvement is explained by a based physics model which describes a variation of the inversion charge centroid towards the buried oxide for large substrate biases. [ABSTRACT FROM PUBLISHER]

This work demonstrates a self-adjustable clock generator that closely tracks the voltage dependence of the critical path delay in a microprocessor. A tunable replica circuit (TRC) composed of inverter cells from the standard-cell library performs real-time frequency modulation to reduce the response time to a single cycle, and a digital controller quantizes the clock frequency by selecting appropriate phases of a delay-locked loop (DLL) that generates 16 phases of 2 GHz output. A watchdog unit continuously monitors the clock output to guard against metastability arising from the asynchronous path between the controller and the DLL. The proposed design is implemented in a 28 nm UTBB FDSOI technology and occupies an area of 1120 \mu \text m^2 with 2.7 mW power consumption. The generator has a wide tuning range of 550–2260 MHz at 1 V, functions at 35 MHz at 0.4 V, and can continuously synthesize the clock signal for arbitrary voltage waveforms between 0.4 V and 1 V. [ABSTRACT FROM PUBLISHER]

Fully depleted SOI (FDSOI) has become a viable technology not only for continued CMOS scaling to 22 nm node and beyond but also for improving the performances of legacy technology when retrofitting to old technology nodes. In this paper, we provide an overview of FDSOI technology, including the benefits and challenges in FDSOI design, manufacturing, and ecosystem. We articulate that FDSOI is potential cornerstone for China to catch up and leapfrog in semiconductor technology. [ABSTRACT FROM AUTHOR]

The versatility of split capacitance measurements on the standard SOI gated p-i-n diodes is presented and discussed. The presence of both n+- and p+-type contacts in the same structure eliminates the floating-body and transient effects, and stands as a major advantage over the conventional MOSFETs characterization. We demonstrate the feasibility of simultaneous electrical (threshold voltage for n- and p-channels) and structural (layer thickness) parameter extraction by systematic measurements and TCAD numerical simulations. [ABSTRACT FROM PUBLISHER]

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology. [ABSTRACT FROM AUTHOR]

An analytical model is proposed to determine the potential and the electron concentration in 1D-confined quantum-well structures. This model is applicable to any kind of asymmetric planar device, such as high-electron-mobility transistors or fully depleted semiconductor-on-insulator FETs. It is based on the solution of the Poisson and Schrödinger equations, under the effective mass approximation, for a triangular potential well, and on the first-order perturbation theory. It is grounded on the physics that governs the device operation and avoids the use of any fitting parameter. The analytical solution considers the wave function penetration into the gate insulator, the effective mass discontinuity at the semiconductor–insulator interfaces, and the Fermi–Dirac statistics. Expressions for the calculation of the subband energies, their corresponding wave functions, as well as the potential profile in the structure are provided. It is demonstrated that our analytical model fits very well the numerical results in all operating regimes from subthreshold to strong inversion for different device sizes and materials. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of the radial ionization profile of proton on SEU sensitivity for nanoscale devices. Intrinsic radial track structures of energy deposition of protons (from 0.5 to 2 MeV) in a silicon box with 2~\mu\m of Si over-layer and a 100-nm silicon film were investigated. The orders of magnitude of the radial deposition is around 200 to 300 nm. Approaches based on punctual or average depositions induce a drift increasing for nanoscale volumes. Realistic energy deposition databases were developed thanks to GEANT4 and coupled with MUSCA SEP3 to perform SEU cross sections and SER estimations. Calculations applied to SOI and bulk technologies (65 and 45-nm) were conducted and compared with experimental results. Calculations are consistent with experiments, despite some drifts. Analyses demonstrate the necessity to consider the 3D morphology description in SEE modeling for nanoscale technologies, more particularly for SOI technologies. [ABSTRACT FROM PUBLISHER]

This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28 nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2 V to 2.4 V with a nominal input voltage of 1 V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottom-plate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1 V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 µA to 500 µA, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation. [ABSTRACT FROM AUTHOR]

MOS bulk transistor is reaching its limits: sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage (VT) and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide (BOx). Called ultra thin body and buried oxide (UTBB) transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator (VCO) based on a ring oscillator (RO) designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about −94 dBc/Hz@1 MHz. [ABSTRACT FROM AUTHOR]

In this study, we investigate the impact of junction doping distribution (LDD/halo) on variations and asymmetry of device characteristics for fully depleted silicon on insulator (FDSOI) with ultrathin buried oxide layer nMOSFET. The device performance and hot carrier induced degradations have also been examined. Junction doping dose of LDD/halo affects the effective channel length, parasitic source/drain resistance, and channel mobility. High junction doping dose enhances the device's performance but degrades device stability and reliability. Compared to high junction doping FDSOI nMOSFET, low junction doping device has lower device variability, better symmetry, and reliability, but suffers lower channel mobility and device driving capability. [ABSTRACT FROM PUBLISHER]

Wide voltage range operation for DSPs brings more versatility to achieve high energy efficiency in mobile applications. This paper describes a 32 bits DSP fabricated in 28 nm Ultra Thin Body and Box FDSOI technology. Body Biasing Voltage (VBB) scaling from 0 V up to ±2 V decreases the core VDDMIN to 397 mV and increases clock frequency by +400%@500 mV and +114%@1.3 V. The DSP frequency measurements show 2.6 GHz@1.3 V(VDD)@2 V(VBB) and 460 MHz@397 mV(VDD)@2 V(VBB). The lowest peak energy efficiency is measured at 62 pJ/op at 0.53 V. In addition to technological gains, maximum frequency tracking design techniques are proposed for wide voltage range operation. On silicon, at 0.6 V, those techniques allow high energy gain of 40.6% w.r.t. a worst case corner approach. [ABSTRACT FROM PUBLISHER]