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This paper presents the design of a ball grid array package and more importantly describes the integration of a microstrip grid array antenna in the package in a low temperature cofired ceramic (LTCC) technology for a single-chip 60-GHz receiver. The grid array package has a small volume of 13.5 × 8 × 1.265 mm3 and can house a 60-GHz receiver die of current size. The package samples were fabricated and measured. The package part demonstrates low insertion loss <; 0.08 dB and excellent matching with return loss >; 22 dB below 5 GHz; while the antenna part achieves good matching (|S11 | ≤ -10 dB), high efficiency (η >; 88%), and directional patterns with the main beam in the boresight direction from 57 to 64 GHz as well as high gain with the peak value of 14.5 dBi at 60 GHz. [ABSTRACT FROM PUBLISHER]

Antenna-on-chip (AoC) and antenna-in-package (AiP) solutions are studied for highly integrated millimeter-wave (mmWave) devices in wireless communications. First, the background, regulations, standard, and applications of 60-GHz wireless communications are briefly introduced. Then, highly integrated 60-GHz radios are overviewed as a basis for the link budget analysis to derive the antenna gain requirement. Next, in order to have deep physical insight into the AoC solution, the silicon substrate's high permittivity and low resistivity effects on the AoC efficiency are examined. It is shown that the AoC solution has low efficiency, less than 12% due to. large ohmic losses and surface waves, which requires the development of techniques to improve the AoC efficiency. After that, the AiP solution and associated challenges such as how to realize low-loss interconnection between the chip and antenna are addressed. It is shown that wire-bonding interconnects, although inferior to the flip-chip, are still feasible in the 60-GHz band if proper compensation schemes are utilized. An example of the AiP solution in a low-temperature cofired ceramic (LTCC) process is presented in the 60-GHz band showing an efficiency better than 90%. A major concern with both AoC and AiP solutions is electromagnetic interference (EMI), which is also discussed. Finally, the systems level pros and cons of both AoC and AiP solutions are highlighted from the electrical and economic perspectives for system designers. [ABSTRACT FROM AUTHOR]

This paper first presents a quasi-cavity-backed, guard-ring-directed, substrate-material-modulated slot antenna. The antenna, intended for use in highly integrated 60-GHz radios, is deliberately designed to exhibit capacitive input impedance to suit low-cost wire-bonding packaging and assembly technique. The antenna implemented in a thin cavity-down ceramic ball grid array (CBGA) package in low-temperature cofired ceramic (LTCC) technology has achieved an acceptable impedance bandwidth from 59 to 65 GHz with an estimated efficiency of 94%. At millimeter-wave (mm-wave) frequency 60 GHz, one of key challenges is how to realize low-loss interconnection between a radio chip and an antenna using wire-bonding technique. This paper then addresses this issue in the framework of antenna-in-package (AiP) design at 60 GHz and proposes a new solution to the challenge. Detailed wirebond design method and results are given. A major concern with AiP is the risk of the antenna coupling to the radio chip. This paper also evaluates this unwanted coupling and shows that the coupling from the in-package antenna to the on-chip inductor is lower than 30 dB for the worst case. These results clearly demonstrate the feasibility and promise of the elegant AiP technology for emerging high-speed short-range 60-GHz wireless communications. [ABSTRACT FROM AUTHOR]

In this paper, a new planar superstrate antenna concept suitable for integration with millimeter wave (mmWave) transceiver integrated circuits (ICs) is presented. The antenna is printed on the bottom of a dielectric superstrate with a ground plane below. The new design provides high bandwidth and high efficiency. Two different examples of the new concept have been designed and manufactured for the 60 GHz industrial scientific medical (ISM) band using folded dipoles. Simulated and measured input impedance matching and far field radiation patterns for both antennas will be shown and discussed. Both designs achieve over 10% bandwidth while maintaining better than 80% efficiency. [ABSTRACT FROM AUTHOR]

In this paper, we present a cost-effective chip-scale packaging solution for a 60-GHz industrial-scientific-medical band receiver (Rx) and transmitter (Tx) chipset capable of gigabit-per-second wireless communications. Envisioned applications of the packaged chipset include 1–3-Gb/s directional links using amplitude shift-keying or phase shift-keying modulation and 500-Mb/s-1-Gb/s omni-directional links using orthogonal frequency-division multiplexing modulation. This paper demonstrates the first fully package-integrated 60-GHz chipset including receive and transmit antennas in a cost-effective plastic package. A direct-chip-attach (DCA) and surface mountable land-grid-array (LGA) package technology is presented. The size of the DCA package is 7 × 11 mm² and the LGA package size is 6 × 13 mm². Optionally, the Tx and Rx chip can be packaged together with Tx and Rx antennas in a combined 13 × 13 mm² LGA transceiver package. [ABSTRACT FROM AUTHOR]

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-µm partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (∼300-Ω·cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 Ω·cm). The VCO occupies a chip area of only 100 µm by 100 µm (excluding pads).

In this paper, a general design methodology of low-voltage wide-band voltage-controlled oscillator (VCO) suitable for wireless LAN (WLAN) application is described. The applications of high-quality passives for the resonator are introduced: 1) a single-loop horseshoe inductor with Q > 20 between 2 and 5 GHz [1] for good phase noise performance; and 2) accumulation MOS (AMOS) varactors with C[sub max]/C[sub min] ratio of 6 [2] to provide wide-band tuning capability at low-voltage supply. The adverse effect of AMOS varactors due to high sensitivity is examined. Amendment using bandswitching topology is suggested, and a phase noise improvement of 7 dB is measured to prove the concept. The measured VCO operates on a 1-V supply with a wide tuning range of 58.7% between 3.0 and 5.6 GHz when tuned between ±0.7 V. The phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz, with the nominal power dissipation between 2 and 3 mW across the whole tuning range. The best phase noise at 1-MHz offset is -124 dBc/Hz at the frequency of 3 GHz, a supply voltage of 1.4 V, and power dissipation of 8.4 mW. When the supply is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz. Using this design methodology, the feasibility of generating two local oscillator frequencies (2.4-GHz ISM and 5-GHz U-NII) for WLAN tranceiver using a single VCO with only one monolithic inductor is demonstrated. The VCO is fabricated in a 0.13-µm partially depleted silicon-on-insulator CMOS process. [ABSTRACT FROM AUTHOR]

In this paper, a 1-V 3.8-5.7-GHz wide-band voltage-controlled oscillator (VCO) in a 0.13-µm silicon-on-insulator (SOI) CMOS process is presented. This VCO features differentially tuned accumulation MOS varactors that: 1) provide 40% frequency tuning when biased between 0-1 V and 2) diminish the adverse effect of high varactor sensitivity through rejection of common-mode noise. This paper shows that, for differential LC VCOs, all low-frequency noise such as flicker noise can be considered to be common-mode noise, and differentially tuned varactors can be used to suppress common-mode noise from being up-converted to the carrier frequency. The noise rejection mechanism is explained, and the technological advantages of SOI over bulk CMOS in this regard is discussed. At 1-MHz offset, the measured phase noise is -121.67 dBc/Hz at 3.8 GHz, and -111.67 dBc/Hz at 5.7 GHz. The power dissipation is between 2.3-2.7-mW, depending on the center frequency, and the buffered output power is -9 dBm. Due to the noise rejection, the VCO is able to operate at very low voltage and low power. At a supply voltage of 0.75 V, the VCO only dissipates 0.8 mW at 5.5 GHz. [ABSTRACT FROM AUTHOR]

An introduction to the special issue on antennas and propagation aspects of 60-90 GHz wireless communications of the journal "IEEE Transactions on Antennas and Propagation" is presented in which the editor discusses an article on the statistical characterization of 60 GHz indoor radio channels by Smulder, the antenna-on-chip (AoC) and antenna-in-package (AiP) solutions to highly integrated millimeter-wave devices by Zhang and Liu, and the use of uniplanar-compact electromagnetic bandgap (EBG) structure (UC-EBG) at 60 GHz by Lamminen and colleagues.

Millimeter and sub-millimeter waves have been the focus of intensive research activities over the past several years. Application of these technologies has advanced beyond traditional high-cost niche uses - mostly related to radio astronomy and space applications - to embrace widespread new consumer applications, some of which show significant market potential. Increased opportunity to exploit these bands is in part created by the spectrum availability that enables extremely high data rates and the inherent miniaturizability of the radio front-ends. This naturally drives concomitant advancements in semiconductor technology at mm-waves and sub-millimeter waves that lower technology deployment cost and make it affordable for applications such as home multi-gigabit wireless systems, active and passive high resolution imaging for medical diagnostic or civil security applications, automotive radar, and body-area networks. [ABSTRACT FROM PUBLISHER]

This article summarizes the development of mature and highly integrated SiGe BiCMOS ICs for gigabit-per-second communications according to the requirements of the IEEE 802.15.3c and 802.11.ad-draft standards. A single-element transceiver chipset for point-to-point communications is described with emphasis on a featurerich yet compact 60-GHz receiver. Next, a 16-element phased-array transceiver chipset for non-line-of-sight communications is described, with emphasis on a new power-efficient phasedarray transmitter. Examples of gigabit-per-second line-of-sight and non-line-of-sight link experiments are provided, and system-level implementation trade-offs are discussed. [ABSTRACT FROM PUBLISHER]