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We have measured the low-frequency 1/ f noise of Si0.55Ge0.45 p MOSFETs with a Si capping layer and SiO2/HfO2/TiN gate stack as a function of frequency, gate voltage, and temperature (100–440 K). The magnitude of the excess drain voltage noise power spectral density ( \textitS {vd} ) is unaffected by negative-bias-temperature stress (NBTS) for temperatures below ~250 K, but increases significantly at higher temperatures. The noise is described well by the Dutta-Horn model before and after NBTS. The noise at higher measuring temperatures is attributed primarily to oxygen-vacancy and hydrogen-related defects in the SiO2 and HfO2 layers. At lower measuring temperatures, the noise also appears to be affected strongly by hydrogen-dopant interactions in the SiGe layer of the device. [ABSTRACT FROM PUBLISHER]

The total ionizing dose response of Ge channel pFETs with raised Si0.55Ge0.45 source/drain is investigated under different radiation bias conditions. Threshold-voltage shifts and transconductance degradation are noticeable only for negative-bias (on state) irradiation, and are mainly due to negative bias-temperature instability (NBTI). Nonmonotonic leakage changes during irradiation are observed, which are attributed to the competition of radiation-induced field transistor leakage and S/D junction leakage. [ABSTRACT FROM PUBLISHER]

We investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The measured activation energies for interface-trap charge buildup during negative-bias temperature stress are lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si–H bonds and that Ge–H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2. [ABSTRACT FROM PUBLISHER]

The constant-voltage electrical stress and 10-keV x-ray irradiation responses of encapsulated graphene-hBN devices are evaluated. Both constant-voltage stress and x-ray exposure induce only modest shifts in the current and the Dirac point of the graphene. Charge trapping at or near the graphene/BN interface is observed after x-ray irradiation. The experimental results suggest that net hole trapping occurs in the BN at low doses and that net electron trapping occurs at higher doses. First-principles calculations also demonstrate that hydrogenated substitutional carbon impurities at B/N sites at or near the graphene/BN interface can play an additional role in the radiation response of these structures. [ABSTRACT FROM PUBLISHER]

Electrical stress and 10-keV x-ray irradiation and annealing responses are evaluated for back-gate MoS2 transistors. Relative stability of device characteristics is observed for constant-voltage stress. The drain current decreases significantly after both positive and negative bias irradiation. Density functional theory calculations and ozone exposure experiments suggest that O atoms adsorbed on the MoS2 surface during 10-keV x-ray irradiation function as electron traps, causing mobility degradation and voltage shifts. [ABSTRACT FROM PUBLISHER]

The total ionizing dose (TID) response of double-gate SiGe-SiO_2/HfO_2 \ pMOS FinFET devices is investigated under different device bias conditions. Negative bias irradiation leads to the worst-case degradation due to increased hole trapping in the HfO_2 layer, in contrast to what is typically observed for devices with SiO_2 or HfO_2 gate dielectrics. This occurs in the devices because radiation-induced holes that are generated in the SiO_2 interfacial layer can transport and become trapped in the HfO_2 under negative bias, leading to a more negative threshold voltage shift than observed at 0 V bias. Similarly, radiation-induced electrons that are generated in the SiO_2 interfacial layer can transport into the HfO_2 and become trapped under positive bias, leading to a more positive threshold voltage shift than observed at 0 V bias. [ABSTRACT FROM PUBLISHER]