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Proportion Integration Differentiation (PID) is a common clock disciplining algorithm. In satellite clock source equipment and in Internet of Things (IoT) sensor nodes it is usually required that both time and frequency signals have high accuracy. Because the traditional PID clock disciplining method used in the equipment only performs PID calculation and feedback control on single variable, such as frequency, the time accuracy error of the clock source is large and even has inherent deviation. By using the integral relationship between frequency and time, a new two variables PID control algorithm for high-precision clock disciplining is proposed in this paper. Time is taken as the constraint variable to make the time deviation converge. It can guarantee a high accuracy of time and high long-term stability of frequency. At the same time, frequency is taken as the feedback variable to make frequency obtain fast convergence. It can ensure high short-term stability of the frequency and the continuity of time. So, it can make the time and frequency of the disciplined clock have high accuracy and stability at the same time. In order to verify the effectiveness of the proposed algorithm, it is simulated based on the GNSS disciplined clock model. The GNSS time after Kalman filtering is used as the time reference to discipline the local clock. The simulation results show that the time deviation range of a local clock after convergence is −0.38 ns∼0.31 ns, the frequency accuracy is better than 1 × 10 − 15 averaging over one day, and the long-term time stability (TDEV) for a day is about 7 ps when using the two variables PID algorithm. Compared with the single variable PID algorithm, the time accuracy of the two variables PID algorithm is improved by about one order of magnitude and the long-term time stability (TDEV) is improved by about two orders of magnitude. The research results indicate that the two variables PID control algorithm has great application potential for the development of clock source equipment and other bivariate disciplining scenarios. [ABSTRACT FROM AUTHOR]

Marine controlled source electromagnetic (MCSEM) method is widely used to reveal the electrical structure of shallow media below the seafloor. It is an indispensable geophysical means in the exploration of marine oil and gas exploration, natural gas hydrates and seafloor geological structures. The transmitter and receiver in electromagnetic detection equipment need to maintain a high temporal consistency, usually using high-stability pulse-per-second (PPS) generated by GPS or BeiDou navigation modules as a synchronization signal. Coaxial cable is a widely used tow cable, so it is necessary to design a clock synchronization method of marine controlled source electromagnetic transmitter using coaxial cable. This paper proposes a method for synchronizing the internal clocks of the transmitter with PPS using ship-borne power supply when coaxial cable is used as tow cable. In this method, the ship-borne high-power supply outputs a high-voltage AC signal that is synchronized with the 400 Hz signal output from GPS; the coaxial cable transmits AC high power electrical energy and control commands; the AC signal transmitted via the coaxial cable is converted into a stable and continuous 1 Hz signal by step-down, waveform shaping and frequency division for synchronizing the internal time pulses of the transmitter. The test result shows that the 1 Hz signal obtained by this method has a deviation of about 504 ns relative to the PPS. This deviation meets the need of MCSEM transmitter for clock synchronization. [ABSTRACT FROM AUTHOR]

Phase alignment of periodic events between multiple systems is required in multiple fields and applications. Most of the existing solutions focus on either low frequency and relatively low accuracy or high complexity, high accuracy and precision. In contrast, this work aimed to develop an intermediate solution, supporting high frequencies and relatively high accuracy and precision, with relatively low complexity. A hypothetical concept and mathematical model is presented with a hardware test implementation based entirely on FPGA resources. Deliberate resource selection and utilization enables a significant simplification of calculations and, as a result, a reduction in logic resource utilization. The proposed concept was implemented and verified using the AMD/Xilinx Artix 7 35T FPGA platform. [ABSTRACT FROM AUTHOR]

Clock synchronization is critically important in positioning, navigation and timing systems. While its performance has been intensively studied in a wide range of disciplines, much less is known for the fundamental thermodynamics of clock synchronization‒what limits the precision and how to optimize the energy cost for clock synchronization. Here, we report the first experimental investigation of two stochastic autonomous clocks synchronization, unveiling the thermodynamic relation between the entropy cost and clock synchronization in an open cavity optomechanical system. Two interacting clocks are synchronized spontaneously owing to the disparate decay rates of hybrid modes by engineering the controllable cavity-mediated dissipative coupling. The measured dependence of the degree of synchronization on the overall entropy cost exhibits an unexpected non-monotonic characteristic, while the relation between the degree of synchronization and the entropy cost for the synchronization is monotonically decreasing. The investigation of transient dynamics of clock synchronization exposes a trade-off between energy and time consumption. Our results demonstrate the possibility of clock synchronization in an effective linear system, reveal the fundamental relation between clock synchronization and thermodynamics, and have a great potential for precision measurements, distributed quantum networks, and biological science. [ABSTRACT FROM AUTHOR]

The inter-satellite link (ISL) has been received increasing attention, as it is a potential way to achieve autonomous clock synchronization for envisioned space-based satellite networks with minimal ground segment capability. Existing satellite clock synchronization solutions either rely on prior information or modelling the relative motion by an approximated polynomial. In this paper, we propose a deep learning approach based on long short-term memory (LSTM) to decouple the clock parameters from pseudo-range measurements. The process of clock parameter estimation solely relies on the observed pseudo-range measurements, and the prior information of position and velocity are not required and the nonlinear relative motion process is modelled by training on historical data. The simulation results show that the proposed method outperforms the benchmark solutions in terms of accuracy. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock's phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps. [ABSTRACT FROM AUTHOR]

Clock synchronization is one of the popular research topics in Distributed Measurement and Control Systems (DMCSs). In most industrial fields, such as Smart Grid and Flight Test, the highest requirement for synchronization accuracy is 1 μs. IEEE 1588 Precision Time Protocol-2008 (PTPv2) can theoretically achieve sub-microsecond accuracy, but it relies on the assumption that the forward and backward delays of PTP packets are symmetrical. In practice, PTP packets will experience random queue delays in switches, making the above assumption challenging to satisfy and causing poor synchronization accuracy. Although using switches supporting the Transparent Clock (TC) can improve synchronization accuracy, these dedicated switches are generally expensive. This paper designs a PTP clock servo for compensating Queue-Induced Delay Asymmetry (QIDA), which can be implemented based on ordinary switches. Its main algorithm comprises a minimum window filter with drift compensation and a fuzzy proportional–integral (PI) controller. We construct a low-cost hardware platform (the cost of each node is within USD 10) to test the performance of the clock servo. In a 100 Mbps network with background (BG) traffic of less than 70 Mbps, the maximum absolute time error (max |TE|) does not exceed 0.35 μs, and the convergence time is about half a minute. The accuracy is improved hundreds of times compared with other existing clock servos. [ABSTRACT FROM AUTHOR]

The Mössbauer rotor effect recently gained a renewed interest due to the discovery and explanation of an additional effect of clock synchronization which has been missed for about 50 years, i.e. starting from a famous book of Pauli, till some more recent experimental analyses. The theoretical explanation of such an additional effect is due to some recent papers in the general relativistic framework. Here, we show that the additional effect of clock synchronization can be calculated in another way via the third postulate of relativity. [ABSTRACT FROM AUTHOR]

Summary: Given the complexity of current supercomputers and applications, being able to trace application executions to understand their behavior is not a luxury. As constraints, tracing systems have to be as little intrusive as possible in the application code and performances, and be precise enough in the collected data. In this article, we present how works the tracing system used by the task‐based runtime system StarPU. We study the different sources of performance overhead coming from the tracing system and how to reduce these overheads. Then, we evaluate the accuracy of distributed traces with different clock synchronization techniques. Finally, we summarize our experiments and conclusions with the lessons we learned to efficiently trace applications, and the list of characteristics each tracing system should feature to be competitive. The reported experiments and implementation details comprise a feedback of integrating into a task‐based runtime system state‐of‐the‐art techniques to efficiently and precisely trace application executions. We highlight the points every application developer or end‐user should be aware of to seamlessly integrate a tracing system or just trace application executions. [ABSTRACT FROM AUTHOR]

IEEE 1588, also known as the Precision Time Protocol (PTP), is a standard protocol for clock synchronization in distributed systems. While it is not architecture-specific, implementing IEEE 1588 on Reduced Instruction Set Computer-V (RISC-V) low-power embedded devices demands considering the system requirements and available resources. This paper explores various approaches and techniques to achieve accurate time synchronization in such instruments. The analysis covers software and hardware implementations, discussing each method's challenges, benefits, and trade-offs. By examining the state-of-the-art in this field, this paper provides valuable insights and guidance for researchers and engineers working on time-critical applications in RISC-V-based embedded systems, aiding in selecting the most-suitable stack for their designs. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of Test & Measurement Technology is the property of Publishing Center of North University of China and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Physics Essays is the property of Physics Essays Publication and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In order to improve clock synchronization precision of the power distribution field network, a power distribution field network with high‐speed power line broadband carrier communication is designed, and a step‐by‐step precision clock synchronization strategy is developed based on modified timing‐sync protocol for sensor networks. In the strategy, the clock of the central node is calibrated in real‐time as the master clock of the field network by the communication master station through the long‐distance communication network, the time and frequency deviations of the clocks of each node in the network are accurately monitored using the broadcast mechanism and the network time base of the carrier communication, and the clock frequency is gradually amended by re‐calibrating the clock temperature compensation coefficient of the node so that the clock of the node is synchronized step‐by‐step within a clock synchronization cycle. The clock synchronization performances of the field network are tested in the laboratory and jobsite, and test results show that the clock synchronization accuracy of the field network is within ± 0.23 s/24 h, which is 28% higher than that of the power distribution field network based on narrowband power line carrier, and these phenomena of time gap or time repetition are avoided in the clock synchronization process. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) aims to revolutionize users’ daily lives by enabling seamless data exchange among various ubiquitous devices over the Internet. However, achieving this broad objective can pose significant challenges for applications that require synchronized timing, such as ensuring the temporal sequencing of data or synchronized performance of activities. IoT networks typically comprise entities with varying resources, making it challenging to implement existing time synchronization methods like N.T.P. (Network Time Protocol) on resource-constrained devices. On the other hand, solutions that work for constrained systems may not be scalable across diverse IoT deployments. This survey paper delves into the clock synchronization issues in IoT installations where applications require a unified perception of time. The article describes clock synchronization solutions for various models and their associated performance and discusses several research challenges related to clock synchronization. Additionally, a review of time synchronization techniques is provided to aid IoT practitioners in selecting the most relevant aspects for deployment. [ABSTRACT FROM AUTHOR]

Copyright of Physics Essays is the property of Physics Essays Publication and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The performance of time-critical systems depends heavily on time synchronization accuracy. Therefore, it is crucial to have a synchronization method that can achieve high time synchronization accuracy. In this paper, we propose a new underlying transmission architecture and new synchronization messages. On the basis of these, aiming at the time error problem of the slave clock, we propose an enhanced time synchronization method based on new synchronization messages. Furthermore, we evaluate the performance of the enhanced time synchronization method on the OMNeT++ simulator. In addition, we compare the impact of different crystal oscillator accuracies and different crystal oscillator frequencies on time synchronization accuracy, respectively. Simulation results show that the time offset is at most ±1 clock period using the enhanced time synchronization method. We realize the purpose of timing the master clock and the slave clock by counting the period of the clock signal. Therefore, we needed to round down the time count to an integer. This is the reason why −1 and 1 appear at the same time. When the crystal oscillator frequency used is 80 MHz, the system can achieve a time synchronization accuracy of ±12.5 ns; that is, a nanosecond-level time synchronization accuracy can be achieved. With the reduction of the crystal oscillator accuracy of the slave clock, the synchronization accuracy of ±1 clock period can still be achieved. With the increase in the crystal oscillator frequency, the time synchronization accuracy that can be achieved also improves. The method proposed in this paper provides a new way of thinking and has certain guiding significance for improving the time synchronization accuracy of time-critical systems. [ABSTRACT FROM AUTHOR]

The rapid development of multi-satellite formations requires inter-satellite radio frequency (RF) measurement to be both precise and scalable. The navigation estimation of multi-satellite formations using a unified time reference demands the simultaneous RF measurement of the inter-satellite range and time difference. However, high-precision inter-satellite RF ranging and time difference measurements are investigated separately in existing studies. Different from the conventional two-way ranging (TWR) method, which is limited by its reliance on a high-performance atomic clock and navigation ephemeris, asymmetric double-sided two-way ranging (ADS-TWR)-based inter-satellite measurement schemes can eliminate such reliance while ensuring measurement precision and scalability. However, ADS-TWR was originally proposed for ranging-only applications. In this study, by fully exploiting the time-division non-coherent measurement characteristic of ADS-TWR, a joint RF measurement method is proposed to obtain the inter-satellite range and time difference simultaneously. Moreover, a multi-satellite clock synchronization scheme is proposed based on the joint measurement method. The experimental results show that when inter-satellite ranges are hundreds of kilometers, the joint measurement system has a centimeter-level accuracy for ranging and a hundred-picosecond-level accuracy for time difference measurement, and the maximum clock synchronization error was only about 1 ns. [ABSTRACT FROM AUTHOR]

Copyright of Electric Power is the property of Electric Power Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Electronic Science & Technology is the property of Electronic Science & Technology Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Clock synchronization is one of the most fundamental and crucial network communication strategies. With the expansion of the Industrial Internet in numerous industrial applications, a new requirement for the precision, security, complexity, and other features of the clock synchronization mechanism has emerged in various industrial situations. This paper presents a study of standardized clock synchronization protocols and techniques for various types of networks, and a discussion of how these protocols and techniques might be classified. Following that is a description of how certain clock synchronization protocols and technologies, such as PROFINET, Time-Sensitive Networking (TSN), and other well-known industrial networking protocols, can be applied in a number of industrial situations. This study also investigates the possible future development of clock synchronization techniques and technologies. [ABSTRACT FROM AUTHOR]

Owing to its unique, concealment and easy customization by combining different wrist and hand gestures, high-density surface electromyogram (HD-sEMG) is recognized as a potential solution to the next generation biometric authentication, which usually adopts a wireless body sensor network (BSN) to acquire the multi-channel HD-sEMG biosignals from distributed electrode arrays. For more accurate and reliable classification, biometric authentication requires the distributed biosignals to be sampled simultaneously and be well aligned, which means that the sampling jitters among the arrays need to be tiny. To synchronize data sampling clocks of a cluster of BSN nodes for biometric authentication, this article modifies the packet-coupled oscillators protocol by using a dynamic controller (D-PkCOs). This protocol only involves one-way single packet exchange, which reduces the communication overhead significantly. For the purpose of maintaining precise sampling of these BSN nodes subject to drifting clock frequency and varying delays, the dynamic controller is designed via the $H_\infty$ robust method, and it is proved that all the BSN nodes’ sampling jitters are bounded. The experimental results demonstrate that the D-PkCOs protocol can keep the sampling jitters less than a microsecond in a 10-node IEEE 802.15.4 network. The application of D-PkCOs to the BSN shows that the HD-sEMG signal with a high signal-to-noise ratio is obtained, which leads to better gesture classification performance. [ABSTRACT FROM AUTHOR]

EtherCAT is one of the preferred real-time Ethernet technologies. However, EtherCAT is not applicable in high-end control fields due to real-time constraints. Clock synchronization and cycle time are the most representative limitations. In this paper, a novel Heterogeneous Parallel System Architecture (HPSA) with features of parallel computation and hard real-time is presented. An HPSA-based EtherCAT hard real-time master is developed to significantly improve clock synchronization and shorten cycle time. Traditional EtherCAT masters feature serial processing and run on a PC. This HPSA-based master consists of two parts: EtherCAT master stack (EMS) and EtherCAT operating system (EOS). EMS implements the parallel operation of EtherCAT to realize the shorter cycle time, and EOS brings a hard real-time environment to the HPSA-based master to improve clock synchronization. Furthermore, this HPSA-based master operates on a heterogeneous System-on-a-chip (SoC). EMS and EOS form a heterogeneous architecture inside this SoC to achieve low-latency process scheduling. Experimental results show that in our HPSA-based EtherCAT hard real-time master, the cycle time reaches the sub-50 μ s range, and the synchronization error reduces to several nanoseconds. Thus, this HPSA-based master has great application value in high-performance control systems. [ABSTRACT FROM AUTHOR]

Modern cars are characterized by a growing number of sensors, actuators, and advanced driver assistance systems that require a synchronized view of the time. These devices are typically interconnected by CAN, which is still the most important in-vehicle network. Precise clock synchronization over CAN is difficult due to the properties of the bus, and current approaches often use dedicated hardware or proprietary software solutions. A few years ago, however, the AUTomotive Open System ARchitecture (AUTOSAR) development alliance published a standardized synchronization method. In this article, we investigate what synchronization precision can be realistically achieved in a real-world automotive hardware and software environment. This involves pure software timestamping, standard CAN controllers without hardware modifications, and a typical automotive real-time operating system. We evaluate several approaches to reduce the synchronization jitter using filtering and optimizing the timestamping procedure. Experiments show that, ultimately, a precision better than 50 $\mu$ s can be achieved with a fully AUTOSAR-compliant software implementation. [ABSTRACT FROM AUTHOR]

The information theoretically secure Kirchhoff-law-Johnson-noise (KLJN) key exchange scheme, similarly to quantum key distribution (QKD), is also potentially vulnerable against clock attacks, where Eve takes over the control of clock synchronization in the channel. This short note aims to introduce a time synchronization protocol scheme for Alice and Bob, which is resistant against arbitrary time delay attacks, both symmetric and asymmetric ones. We propose and explore various ways of clock synchronization for the KLJN system and propose an ultimate protocol that preserves time and hardware integrity under arbitrary attacks. [ABSTRACT FROM AUTHOR]

In modern medicine, smart wireless connected devices are gaining an increasingly important role in aiding doctors’ job of monitoring patients. More and more complex systems, with a high density of sensors capable of monitoring many biological signals, are arising. Merging the data offers a great opportunity for increasing the reliability of diagnosis. However, a huge problem is constituted by synchronization. Multi-board wireless-connected monitoring systems are a typical example of distributed systems and synchronization has always been a challenging issue. In this paper, we present a distributed full synchronized system for monitoring patients’ health capable of heartbeat rate, oxygen saturation, gait and posture analysis, and muscle activity measurements. The time synchronization is guaranteed thanks to the Fractional Low-power Synchronization Algorithm (FLSA). [ABSTRACT FROM AUTHOR]

Clock synchronization provides fundamental timing reference for various services in the Internet of Things. Unlike centralized synchronization algorithm, which relies heavily on the synchronization routing and brings about error accumulation consequently, the distributed synchronization algorithm achieves clock synchronization through time message exchange and calculation among adjacent nodes, hence the error accumulation can be greatly eliminated. However, the convergence speed of existing distributed synchronization algorithms is generally slow, and network topology information is seldom utilized to improve the convergence speed, which may cause additional energy consumption, especially in resource-constrained scenarios. To improve the convergence speed of distributed clock synchronization, a consensus tracking-based clock synchronization (CTCS) algorithm is proposed in this paper. By analyzing the synchronization process in the state space framework, the convergence acceleration term is designed to optimize the eigenvalue distribution of synchronization error matrix, hence the convergence speed can be greatly improved. To be suitable for clock synchronization in the dynamic network, a reference clock input term is designed in the clock update formula, which eliminates the oscillation of synchronized clocks triggered by synchronization of newly joined nodes. To prove the convergence of CTCS, an in-depth analysis of the algorithm is conducted. Both simulation and experimental results validate the effectiveness of CTCS in comparison with other solutions. [ABSTRACT FROM AUTHOR]

Time triggered communication provides fault tolerance and determinism in a distributed dependable real time systems. These systems crucially depend on fault tolerant clock synchronization. The article presents simulation of fault tolerant averaging algorithm for clock synchronization and it's modification for improved convergence. We present the simulation results of synchronization algorithm to verify fault tolerance and convergence to a single time base. By modification, we show how a two node system can also be synchronized eliminating the criteria of minimum three nodes. This article also reports a custom time triggered protocol named as deterministic fault tolerant communication protocol particularly suitable for mission critical applications or safety-critical control applications such as in automotive “by-wire” and aerospace systems. The article also presents a different approach for membership service which is based on majority voting and can be used in systems based on time triggered architecture. [ABSTRACT FROM AUTHOR]

In wireless application, mobile low duty cycle wireless sensor network (MLDC‐WSN) gained more attention among the researchers, because it includes advantages like growing node life, saving node power, and network reliability. However, the sleeping features and mobility of MLDC‐WSN results in topology change that restricts the speed of neighbor node discovery. To highlight this concern, a novel routing protocol named as improved Bayesian clock synchronization‐gossip routing protocol is proposed for an effective neighbor node discovery in MLDC‐WSN. The proposed routing protocol reduces end‐to‐end delay, and clock drifts problems. Also, the proposed routing protocol improves the clock synchronization and captures the neighbor discovery nodes by identifying the next neighbor set in the next moment, due to the prediction of the distance and movement speed of neighbors. Simulation and analytical results showed that the proposed routing protocol superiorly decreases the end‐to‐end delay and energy consumption compared to the existing algorithms. [ABSTRACT FROM AUTHOR]

Industrial control systems present numerous challenges from the communication systems perspective: clock synchronization, deterministic behavior, low latency, high reliability, flexibility, and scalability. These challenges are mostly solved with standard technologies over Ethernet, e.g., time-sensitive networking (TSN). As a research trend, it is expected that TSN will converge with wireless, leading to the Wireless TSN paradigm. Also, Wireless TSN is expected to be integrated with Ethernet TSN to create large-scale wired–wireless (Hybrid) TSN networks. The first step toward Hybrid TSN is the distribution of the clock reference from the wired to the wireless domain. In this article, we leverage existing Ethernet TSN and wireless technologies implementations (Wi-Fi and w-SHARP) and present two hardware architectures specifically engineered to enable the clock synchronization distribution among the network domains. The hardware architectures have been implemented over a system-on-chip field-programmable gate array platform. We demonstrate through several experiments that the implementation is able to fulfill the synchronization performance required by TSN. [ABSTRACT FROM AUTHOR]

Nowadays, smartphones can produce a synchronized (synced) stream of high-quality data, including RGB images, inertial measurements, and other data. Therefore, smartphones are becoming appealing sensor systems in the robotics community. Unfortunately, there is still the need for external supporting sensing hardware, such as a depth camera precisely synced with the smartphone sensors. In this paper, we propose a hardware-software recording system that presents a heterogeneous structure and contains a smartphone and an external depth camera for recording visual, depth, and inertial data that are mutually synchronized. The system is synced at the time and the frame levels: every RGB image frame from the smartphone camera is exposed at the same moment of time with a depth camera frame with sub-millisecond precision. We provide a method and a tool for sync performance evaluation that can be applied to any pair of depth and RGB cameras. Our system could be replicated, modified, or extended by employing our open-sourced materials. [ABSTRACT FROM AUTHOR]

Among the flooding-based time synchronization protocols in wireless sensor networks, rapid-flooding outperforms slow-flooding in terms of synchronization speed. However, sometimes it is not realistic to apply rapid-flooding in dense or low-duty cycle networks due to its operational constraint that timing messages must be forwarded immediately after being received. On the contrary, slow-flooding protocols are free from this operational constraint, but they have a fundamental limitation that their convergence time increases with the size of the network. In this letter, we prove that this limitation can be overcome by sharing the compensated skew and timing information to the next hop nodes so that they can all be synchronized in the same round. The evaluation results demonstrate that we can achieve a comparable convergence speed of rapid-flooding protocols with the slow-flooding-based mechanism and can provide better accuracy for network-wide and per-hop synchronization. [ABSTRACT FROM AUTHOR]

The Mössbauer rotor effect recently gained a renewed interest due to the discovery and explanation of an additional effect of clock synchronization which has been missed for about 50 years, i.e. starting from a famous book of Pauli, till some recent experimental analyses. The theoretical explanation of such an additional effect is due to some recent papers in both the general relativistic and the special relativistic frameworks. In the first case (general relativistic framework) the key point of the approach is the Einstein’s equivalence principle (EEP), which, in the words of the same Einstein, enables “the point of view to interpret the rotating system K’ as at rest, and the centrifugal field as a gravitational field”. In this paper, we analyse both the history of the Mössbauer rotor effect and its interpretation from the point of view of Einstein’s general theory of relativity (GTR) by adding some new insight. In particular, it will be shown that, if on one hand the “traditional” effect of redshift has a strong analogy with the gravitational redshift, on the other hand the additional effect of clock synchronization has an intriguing analogy with the cosmological redshift. Finally, we show that a recent claim in the literature that the second effect of clock synchronization does not exist is not correct. [ABSTRACT FROM AUTHOR]

Optical switching has attracted significant attention in recent research on data center networks (DCNs) as it is a promising viable route for the further scaling of hyper scale data centers, so that DCNs can keep pace with the rapid growth of machine-to-machine traffic. It has been shown that optical clock synchronization enables sub-nanosecond clock and data recovery time and is crucial to high performance optically switched DCN. Moreover, the interconnect data rate is expected to increase from the current 100 Gb/s per fiber to scale to 800 Gb/s and beyond, requiring high baud rate signaling at >50 GBd. Thus, future optically switched DCN should support >50 GBd data transmission with optical clock synchronization. Here, we demonstrate the clock-synchronized transmission of 128-byte optical packets at 51.2 GBd and study the impact of reference clock phase noise on system performance, focusing on the tolerance to the clock phase misalignment that affects the system scalability and reliability. By comparing the tolerable sampling clock phase offsets using different reference clocks, we show that a clock phase offset window of about 8 ps could be achieved with a <0.2ps source clock. Furthermore, we model and numerically study the de-correlation of clock phase noise. This allows the total jitter to be estimated, and thereby, the estimation of the transmission performance for future generations of high baud rate, clock synchronized DC interconnects. [ABSTRACT FROM AUTHOR]

Optical switching could enable data center networks to keep pace with the rapid growth of intra-data center traffic, however, sub-nanosecond clock and data recovery time is crucial to enabling optically-switched data center networks to transport small packet dominated data center traffic with over 90% efficiency. We review the clock-synchronized approach to clock and data recovery, which enables sub-nanosecond switching time in optically switched networks. We then introduce an analytical model to mathematically explore the operation of clock phase caching, and use this model to explore the impact of factors such as fiber temperature, clock jitter and symbol rate on the BER and clock and data recovery locking time performance of the clock phase caching approach, as well as their impact on scalability. Using commercial data center parameters matching those used in our previous experimental research, we find that our analytical model provides estimates that closely match our previous experimental results, validating its use for making predictions of the performance of clock phase cached systems. [ABSTRACT FROM AUTHOR]

System-level timing fluctuations caused by unstable low-cost clocks and end-to-end communication delays are the main sources of uncertainties in existing synchronization mechanisms that rely on timestamp exchanges. This paper introduces a timestamp-free clock syntonization approach, carrier frequency offset (CFO)-assisted syntonization (CFOSynt), to estimate the clock skew between a pair of nodes by utilizing carrier frequency offset. To enable CFOSynt, we leverage the fact that RF oscillators in the radio can be used as the reference to calibrate the system clock oscillators, and the pairwise RF clock information is carried in the transmission carrier frequency. By incorporating CFO and capturing the clock frequency relationship in system clock skew estimation, CFOSynt can eliminate the need for timestamping and the impact of delay uncertainties. To validate the design, CFOSynt is implemented on two common off-the-shelf (COTS) IoT platforms with access to the CFO estimation from the radio chip. Extensive experiments are conducted to evaluate CFOSynt, and CFOSynt can estimate the clock skew of 32 kHz low-cost electronic oscillators with a mean error of $-2.46$ - 2. 46 Hz. In comparison with timestamp-based approaches, CFOSynt achieves up to 70-90 percent improvement in skew estimation error and shows significant reliability when low-cost oscillators are used. [ABSTRACT FROM AUTHOR]

Inspired by excellent precision of carrier phase positioning, this paper presents a new carrier phase positioning technique for 5G new radio cellular networks with a focus on clock synchronization and integer ambiguity resolution. A carrier-phase based clock offset estimation method is first proposed to achieve precise clock synchronization among base stations, and proved to achieve the Cramér–Rao Lower Bound (CRLB) asymptotically. A fusion method is developed to fuse the estimated positions of a mobile station (MS) based on time-difference-of-arrival, with the estimated position changes based on the temporal changes of carrier phase measurements. While circumventing the integer ambiguities of the carrier phase measurements, the fusion method provides quality interim estimates of the MS positions, at which the measurements can be linearized to resolve the integer ambiguities. As a result, precise MS positions can be obtained based on the disambiguated carrier phase measurements. Numerical simulations show that the proposed carrier phase positioning can achieve a centimeter-level accuracy in wireless cellular networks. [ABSTRACT FROM AUTHOR]

Recent advances in the industrial internet of things (IIoT) and cyber–physical systems drive Industry 4.0 and have led to remote monitoring and control applications that require factories to be connected to remote sites over wide area networks (WAN). The adequate performance of remote applications depends on the use of a clock synchronization scheme. Packet delay variations adversely impact the clock synchronization performance. This impact is significant in WAN as it comprises wired and wireless segments belonging to public and private networks, and such heterogeneity results in inconsistent delays. Highly accurate, hardware–based time synchronization solutions, global positioning system (GPS), and precision time protocol (PTP) are not preferred in WAN due to cost, environmental effects, hardware failure modes, and reliability issues. As a software–based network time protocol (NTP) overcomes these challenges but lacks accuracy, the authors propose a software–based clock synchronization method, called CoSiWiNeT, based on the random sample consensus (RANSAC) algorithm that uses an iterative technique to estimate a correct offset from observed noisy data. To evaluate the algorithm's performance, measurements captured in a WAN deployed within two cities were used in the simulation. The results show that the performance of the new algorithm matches well with NTP and state–of–the–art methods in good network conditions; however, it outperforms them in degrading network scenarios. [ABSTRACT FROM AUTHOR]

This paper studies the secure and accurate clock synchronization problem for sensor networks with time-varying delays and malicious attacks. A novel clock synchronization scheme based on the attack detection mechanism, attack compensation, and maximum consensus protocol is proposed. The proposed scheme starts with the detection of the malicious attacks and the clock data under attacks is eliminated. On the basis, software clock parameters are updated so that all the nodes in the network can have the same software skew and offset, so the clock synchronization can be achieved. Furthermore, it is theoretically proved that the proposed scheme can achieve the attack detection correctly, and further can guarantee a secure and accurate clock synchronization. In addition, extensive simulations are also conducted to validate the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

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Molecular communication (MC) is a promising paradigm, which conveys messages at the nano- or micro- scale for information exchange by using molecules or particles as signal carriers. Clock synchronization between transmitters and receivers in MC systems plays an important role in information exchange and nanodevices’ collaboration. The current research about the synchronization mainly focuses on fixed MC systems. However, the movements of transmitters and receivers commonly exist in MC systems. In this paper, two clock synchronization schemes, the least square method and the peak time method, are proposed to estimate the clock offset between a mobile transmitter and a mobile receiver in mobile MC systems. The synthesis time of information molecules is also taken into consideration in the proposed schemes, and by using different types of molecules, the influence of the synthesis time of molecules can be solved. The effects of the movement of receiver on the received signal are discussed. The performance of the proposed schemes is evaluated by simulations and discussed. [ABSTRACT FROM AUTHOR]

Clock synchronization is crucial for applications in wireless sensor networks, such as event scheduling and data fusion. In practical wireless networks, environmental changes cause the oscillator to be imperfect. Thus, it is necessary to track the nonlinear varying clock dynamically. In this paper, we propose a timestamp-free clock skew (frequency difference) and offset (time difference) joint tracking algorithm based on extended Kalman filter (EKF), which can be embedded into the general network data flow to achieve long-term synchronization without additional communication overhead. To further improve energy efficiency of clock synchronization, this paper develops an EKF clock skew tracking algorithm for silent nodes in receiver-only synchronization. For the situation that silent node overhears synchronization information from multiple active nodes, we present multi-information timestamp-free synchronization and multi-observation clock skew fusion scheme for silent nodes. Simulation results show the effectiveness of the proposed tracking algorithms. [ABSTRACT FROM AUTHOR]

In view of the problem that the current asynchronous network update method takes a long time to update and can not avoid updating deadlock, in order to reduce the network performance loss during updating, a time-based update method for airborne network of aviation swarm is proposed. Considering the real link delay, the time parameter is combined with the update dependency graph. Firstly, a time-based update dependency graph is constructed. Secondly, a greedy scheduling algorithm is designed to allocate the update time step for each update operation. Finally, the timed network update is realized and the update sequence coordination in asynchronous update is avoided. Simulation experiments show that compared with the existing asynchronous updating methods, the update time can be reduced by 50%~60% through the proposed timing update method, and the update deadlock rate and the network congestion are reduced during the network update. [ABSTRACT FROM AUTHOR]

The quantum positioning system (QPS) takes advantage of the entanglement property of the quantum system itself, and it is possible to breakthrough the limitation of the positioning accuracy due to signal bandwidth and power limitation in classical radio-based global positioning system (GPS), and improve the positioning performance. In this paper, a comprehensive survey of the research status of QPS and its several key components are presented, including the quantum entanglement states preparation, the quantum satellite technique, the optical signal acquisition, tracking and pointing (ATP) system, and the quantum positioning and clock synchronization technique. We also discuss the current challenges and future research directions at the end of the paper. [ABSTRACT FROM AUTHOR]

With the rapid development, Wireless Sensor Networks (WSNs) technology has been widely applied in many fields, such as military intelligence detection, medical condition detection, urban facility construction and smart home, etc. Clock synchronization is one of the key technologies in WSNs, precise node time synchronization is critical for many networked control applications in WSNs. Once the clock of sensor nodes loses synchronization, the information collected by nodes will lose timeliness and value for users. Therefore, the key technology of clock synchronization plays an important role in WSNs. The main purpose of clock synchronization is to control the interval time that between sending and receiving timestamps of wireless sensor nodes within acceptable clock synchronization accuracy. However, because there are many kinds of link delays in the process of information transmission, the transmission time is prolonged and the time precision is reduced. Therefore, it is necessary to study the exact causes and effects of these errors. In ZigBee wireless sensor network, through theoretical model and data experimental analysis, we got the result that the random delay distributions of the uplink and downlink obey normal distribution when the sensor nodes exchange some information. [ABSTRACT FROM AUTHOR]

The EDF (Earliest Deadline First) scheduling policy can take advantage of the existence of a synchronization clock mechanism to reach higher utilizations in distributed real-time systems, as indicated by theoretical research. In this work, we give the first steps to enable the usage of EDF and a global clock in a distributed system. To this end, our proposal relies on Linux to provide the global clock and on a Real-Time Operating System (RTOS) to provide the global EDF policy. The objective is the evaluation of global EDF to verify to what extent the theoretical results are met. [ABSTRACT FROM AUTHOR]

Without any dummy element for phase compensation, a clock-deskewing circuit (CDC) using a master–slave delay-locked loop (MSDLL) configuration is presented to synchronize the clocks for cascaded core-to-core links. The dual-locking CDC provides mismatch-insensitive compensation of interconnected wires, input/outputs (IOs), and clock buffers. The MSDLL incorporates the digital-selection folded coarse-fine voltage-controlled delay line (FCF-VCDL) to provide a wide range operations. The proposed FCF-VCDL scheme is constructed from the combination of positive and negative gains of different VCDLs. In addition, a power-controlled regime is employed in the FCF-VCDL to adaptively lower the power dissipation. Implemented with 0.18 μm CMOS, the CDC can provide 20 MHz to 2 GHz with the help of FCF-VCDLs. The 2-GHz clock jitter is 6.78 ps (pk-pk), and the total power dissipation is 20 mW under a 1.8-V supply. [ABSTRACT FROM AUTHOR]

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second signals (PPS). The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication. [ABSTRACT FROM AUTHOR]

The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process–voltage–temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to 64 × 64 pixels over an area of 2.4 × 2.4 cm2 using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution. [ABSTRACT FROM AUTHOR]