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The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2nd-order hybrid-CTDT Δ∑-∑ modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional Δ∑ modulator, while employing an extra ∑-stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18-μm CMOS process and achieves a peak SNR of 105.6 dB and a dynamic range of 108.3 dB, for a maximum input range of 720 mVpp. The measured input-referred noise is 0.98 μVrms over a bandwidth of 0.5–100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts. [ABSTRACT FROM AUTHOR]

Large-scale in vivo electrophysiology requires tools that enable simultaneous recording of multiple brain regions at single-neuron level. This calls for the design of more compact neural probes that offer even larger arrays of addressable sites and high channel counts. With this aim, we present in this paper a quad-shank approach to integrate as many as 5,120 sites on a single probe. Compact fully-differential recording channels were designed using a single-gain-stage neural amplifier with a 14-bit ADC, achieving a mean input-referred noise of 7.44 μVrms in the action-potential band and 7.65 μVrms in the local-field-potential band, a mean total harmonic distortion of 0.17% at 1 kHz and a mean input-referred offset of 169 μV. The probe base incorporates 384 channels with on-chip power management, reference-voltage generation and digital control, thus achieving the highest level of integration in a neural probe and excellent channel-to-channel uniformity. Therefore, no calibration or external circuitry are required to achieve the above-mentioned performance. With a total area of 2.2 × 8.67 mm2 and a power consumption of 36.5 mW, the presented probe enables full-system miniaturization for acute or chronic use in small rodents. [ABSTRACT FROM AUTHOR]

This paper presents a complete 256-electrode retinal prosthesis chip, which is small and ready for packaging and implantation. It contains 256 separate programmable drivers dedicated to 256 electrodes for flexible stimulation. A 4-wire interface is employed for power and data transmission between the chip and a driving unit. Power and forward data are recovered from a 600 kHz differential signal, while backward data are sent at 100 kbps rate simultaneously. The stimulator possesses many stimulation features, supporting various stimulation strategies. Many safety features are included such as real-time monitoring of voltage compliance and temperature, electrode self-locking in the event of out-of-compliance, and ESD protection circuit at every electrode. The chip is fabricated in a 65 nm CMOS process. The electrode driver pitch is 150 µm, and total chip area is 8 mm 2 . The chip has been extensively tested and all the requirements have been successfully verified. The measured DC current error for single driver stimulation without electrode shorting is 20 nA. The average power consumption per electrode with typical stimulus pulse parameters and full-scale output current is 129 µW, inclusive of all standby power. The chip overall power efficiency is 70% with 23 mW of power delivered to load. [ABSTRACT FROM AUTHOR]

Ensuring safe operation of stimulators is the most important issue in neural stimulation. Safety, in terms of stimulators' electrical performances, can be related mainly to two factors; the zero-net charge transfer to tissue and the heat generated by power dissipation at tissue. This paper presents a safety ensuring neuro-stimulator for retinal vision prostheses, featuring precise charge balancing capability and low power consumption, using a 0.35 \mum HV (high voltage) CMOS process. Also, the required matching accuracy of the biphasic current pulse for safe stimulation is mathematically derived. Accurate charge balance is achieved by employing a dynamic current mirror at the output of a stimulator. In experiments, using a simple electrode model (a resistor (R) and a capacitor (C) in parallel), the proposed stimulator ensures less than 30 nA DC current flowing into tissue over all stimulation current ranges (32 \muA–1 mA), without shorting. With shorting enabled, further reduction is achieved down to 1.5 nA. Low power consumption was achieved by utilising small bias current, sharing of key biasing blocks, and utilising a short duty cycle for stimulation. Less than 30 \muW was consumed during stand-by mode, mostly by bias circuitry. [ABSTRACT FROM PUBLISHER]

Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. Second, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. A variation of this include passive charge recovery for further power reduction. In combination, significant implant power consumption reduction is achieved. [ABSTRACT FROM AUTHOR]