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The relationship between edge placement error (EPE), semiconductor design-rule determination, and predicted yield in the era of EUV lithography is examined, starting with the basics of EPE and then building up to design-rule calculations. The EPE definitions can be used as the building blocks for design-rule equations. Next the concept of "good fields" is explored and used to predict the n-sigma value needed for design-rule determination. Specifically, fundamental yield calculations based on the failure opportunities per chip are used to determine at what n-sigma value design-rules need to be tested to ensure high yield. The "value" can be a space between two features, an intersect area between two features, a minimum area of a feature, etc. It is shown that across-chip variation of design-rule important values needs to be tested at sigma values between seven and eight, which is much higher than the 4-sigma values traditionally used for design-rule determination. After recommending new statistics be used for design-rule calculations, we examine the impact of EUV lithography on sources of variation important for design-rule calculations. [ABSTRACT FROM AUTHOR]

Vote-taking lithography is a method for mitigating mask defects, which has been applied in the 1980s to enhance yield. Vote-taking sums up N different mask images with identical content, each at 1/N dose, to mitigate the defects on each individual mask. The fundamental assumption is that the mask defects do not correlate in position from mask to mask, and so each individual defect will be blended with good images from the other N - 1 masks. Vote-taking has recently been reconsidered for extreme ultraviolet (EUV) lithography, where it might provide a temporary solution for situations in which the defectivity conditions are not yet meeting expectations. This paper provides a thorough experimental assessment of the implementation of vote-taking and discusses its pro's and con's. Based on N = 4 vote-taking, we demonstrate the capability to mitigate different types of mask defects. We found additional benefits of blending different mask images, distinct from mask defect reduction. Experimental results will be shown that demonstrate improved critical dimension uniformity (CDU), both local CDU and intrafield CDU, reduced overlay errors, and smaller stochastic defect levels. Finally, we perform dedicated throughput calculations based on the qualification performance of ASML's NXE:3400B scanner. This work must be seen in the light of an open-minded search for options to optimally enable and implement EUV lithography. Although defect-free masks and EUV pellicles are without argument essential for most of the applications, we investigate whether some applications could benefit from vote-taking. [ABSTRACT FROM AUTHOR]

As more aggressive EUV imaging techniques and resists with lower intrinsic roughness are developed for patterning at 7- and 5-nm technology nodes, EUV mask roughness will contribute an increasing portion of the total printed line-width roughness (LWR). We perform a comprehensive characterization of the EUV mask impacts on wafer LWR using actinic aerial images and wafer SEM images. Analytical methods are developed to properly separate and compare the LWR effects from EUV masks, photon shot noise, and resist stochastics. The use of EUV AIMS? to emulate and measure incident photon shot noise effects is explored and demonstrated. A sub 10-nm EUV mask is qualified using EUV AIMS? with scanner equivalent dose settings that are required for patterning 16- and 18-nm half-pitch L/S features. Typical chemically amplified EUV resists with low- and high-dose sensitivities are patterned and characterized with SEM metrology. The variance and spectral components contributing to wafer LWR are quantified and compared. Our analysis shows that speckle-induced aerial LWR is not a significant factor at the experimental imaging conditions when ML roughness is 50-pm rms. At the current scanner dose levels, mask absorber pattern roughness is a major factor in aerial LWR, but not as significant a contributor to wafer LWR where resist stochastics still dominate. [ABSTRACT FROM AUTHOR]

In optical lithography for microchip manufacturing, it is important that the focal ranges of all patterns in the layout be closely aligned in order to maximize a common process window. In practice, large pattern-dependent variations in the position of the best focus are observed, which have been traced back to phase errors induced on the image-forming beams by scattering from mask topography. We show that this degradation mechanism can be exploited as a source of corrective phase shift, allowing pattern-dependent focus shifts to be controlled purely by changing the details of the mask layout, without requiring a significant change in the mask-making process. Phase distortions in the imaging beams are corrected by the optimized insertion of orthogonally oriented subresolution jogs into existing edges in the layout, thereby introducing a tailored scatter contribution whose quadrature component has the opposite sign from that of the primary edge [ABSTRACT FROM AUTHOR]

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors. [ABSTRACT FROM AUTHOR]

A dose-focus monitoring technique using a critical-dimension scanning electron microscope (CD-SEM) is studied for applications on product wafers. Our technique uses two target structures: one is a dense grating structure for dose determination, and the other is a relatively isolated line grating for focus determination. These targets are less than 6 µm, and they can be inserted across a product chip to monitor dose and focus variation in a chip. Monitoring precision is estimated to be on the order of 1% for dose and 10 nm for focus, and the technique can be applied to dose and focus monitoring on product wafers. The developed technique is used to analyze spatial correlation in dose and focus over a wide range of distances, using a mask with a multitude of these targets. The variation (3σ) of dose and focus difference between two monitor targets is examined for various separation distances, and the variation of focus difference increases from 10 to 25 nm as the separation distance increases from ~20 µm to ~10 mm. The variation of 10 nm observed at the shortest distance reflects focus monitoring precision, and focus variation sources such as wafer thickness variation come into play at longer distances. [ABSTRACT FROM AUTHOR]