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Power management (PM) is cumbersome for today's computing systems. Attainable performance is bounded by the architecture's computing efficiency and capped in temperature, current, and power. PM is composed of multiple interacting layers. High-level controllers (HLCs) involve application-level policies, operating system agents (OSPMs), and PM governors and interfaces. The application of high-level control decisions is currently delegated to an on-chip power management unit executing tailored PM firmware routines. The complexity of this structure arises from the scale of the interaction, which pervades the whole system architecture. This paper aims to characterize the cost of the communication backbone between high-level OSPM agents and the on-chip power management unit (PMU) in high performance computing (HPC) processors. For this purpose, we target the System Control and Management Interface (SCMI), which is an open standard proposed by Arm. We enhance a fully open-source, end-to-end FPGA-based HW/SW framework to simulate the interaction between a HLC, a HPC system, and a PMU. This includes the application-level PM policies, the drivers of the operating system-directed configuration and power management (OSPM) governor, and the hardware and firmware of the PMU, allowing us to evaluate the impact of the communication backbone on the overall control scheme. With this framework, we first conduct an in-depth latency study of the communication interface across the whole PM hardware (HW) and software (SW) stack. Finally, we studied the impact of latency in terms of the quality of the end-to-end control, showing that the SCMI protocol can sustain reactive power management policies. [ABSTRACT FROM AUTHOR]

In this work, we target the efficient implementation of spiking neural networks (SNNs) for low-power and low-latency applications. In particular, we propose a methodology for tuning SNN spiking activity with the objective of reducing computation cycles and energy consumption. We performed an analysis to devise key hyper-parameters, and then we show the results of tuning such parameters to obtain a low-latency and low-energy embedded LSNN (eLSNN) implementation. We demonstrate that it is possible to adapt the firing rate so that the samples belonging to the most frequent class are processed with less spikes. We implemented the eLSNN on a microcontroller-based sensor node and we evaluated its performance and energy consumption using a structural health monitoring application processing a stream of vibrations for damage detection (i.e. binary classification). We obtained a cycle count reduction of 25% and an energy reduction of 22% with respect to a baseline implementation. We also demonstrate that our methodology is applicable to a multi-class scenario, showing that we can reduce spiking activity between 68 and 85% at iso-accuracy. [ABSTRACT FROM AUTHOR]

High-performance computing (HPC) processors are nowadays integrated cyber-physical systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multi-core programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multi-core cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant's thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry-grade control algorithm under computational-intensive workloads. [ABSTRACT FROM AUTHOR]

Industrial Architecture and their associated engineering structures have a clear objective. They need to be designed and constructed to allow for a product production independently of their nature. In the early XX century German Architecture, especially with the "Bauhaus" movement and others, such as Pier Luigi Nervi in Italy, provided a great impulse to the concept of Industrial Architecture constituting pieces of art. Today, we find examples of industrial buildings that are excellently preserved, and the management of their changing flexibility demand generate engineering judgement to accommodate new "production options" with a safe performance. [ABSTRACT FROM AUTHOR]

Background Cefiderocol is a novel siderophore cephalosporin with promising activity against most carbapenem-resistant Gram-negative bacteria (CRGNB). However, extensive postmarketing experiences are lacking. This study aimed to analyse the early experience on cefiderocol postmarketing use at three tertiary care hospitals in Italy. Methods We retrospectively included patients with infections caused by CRGNB treated with cefiderocol at three Italian tertiary care hospitals from 1 March 2021 to 30 June 2022. A multivariate Cox model was used to identify predictors of 30 day mortality. A propensity score (PS) analysis with inverse probability weighting (IPW) was also performed to compare the treatment effect of cefiderocol monotherapy (CM) versus combination regimens (CCRs). Results The cohort included 142 patients (72% male, median age 67 years, with 89 cases of Acinetobacter baumannii infection, 22 cases of Klebsiella pneumoniae , 27 cases of Pseudomonas aeruginosa and 4 of other pathogens). The 30 day all-cause mortality was 37% (52/142). We found no association between bacterial species and mortality. In multivariate analysis, a Charlson Comorbidity Index >3 was an independent predictor of mortality (HR 5.02, 95% CI 2.37–10.66, P  < 0.001). In contrast, polymicrobial infection (HR 0.41, 95% CI 0.21–0.82, P  < 0.05) was associated with lower mortality. There was no significant difference in mortality between patients receiving CM (n  = 70) and those receiving a CCR (n  = 72) (33% versus 40%, respectively), even when adjusted for IPW-PS (HR 1.11, 95% CI 0.63–1.96, P  = 0.71). Conclusions Real-life data confirm that cefiderocol is a promising option against carbapenem-resistant Gram-negative infections, even as monotherapy. [ABSTRACT FROM AUTHOR]

Supercomputers are the most powerful computing machines available to society. They play a central role in economic, industrial, and societal development. While they are used by scientists, engineers, decision-makers, and data-analyst to computationally solve complex problems, supercomputers and their hosting datacenters are themselves complex power-hungry systems. Improving their efficiency, availability, and resiliency is vital and the subject of many research and engineering efforts. Still, a major roadblock hinders researchers: dearth of reliable data describing the behavior of production supercomputers. In this paper, we present the result of a ten-year-long project to design a monitoring framework (EXAMON) deployed at the Italian supercomputers at CINECA datacenter. We disclose the first holistic dataset of a tier-0 Top10 supercomputer. It includes the management, workload, facility, and infrastructure data of the Marconi100 supercomputer for two and half years of operation. The dataset (published via Zenodo) is the largest ever made public, with a size of 49.9TB before compression. We also provide open-source software modules to simplify access to the data and provide direct usage examples. [ABSTRACT FROM AUTHOR]

Introduction: Despite the important diagnostic role of peripheral blood morphology, cell classification is subjective. Automated image-processing systems (AIS) provide more accurate and objective morphological evaluation. The aims of this multicenter study were the evaluation of the intra and inter-laboratory variation between different AIS in cell pre-classification and after reclassification, compared with manual optical microscopy, the reference method. Methods: Six peripheral blood samples were included in this study, for each sample, 70 May-Grunwald and Giemsa stained PB smears were prepared from each specimen and 10 slides were delivered to the seven laboratories involved. Smears were processed by both optical microscopy (OM) and AIS. In addition, the assessment times of both methods were recorded. Results: Within-laboratory Reproducibility ranged between 4.76% and 153.78%; between-laboratory Precision ranged between 2.10% and 82.2%, while Total Imprecision ranged between 5.21% and 20.60%. The relative Bland Altman bias ranged between -0.01% and 20.60%. The mean of assessment times were 326 ± 110 s and 191 ± 68 s for AIS post reclassification and OM, respectively. Conclusions: AIS can be helpful when the number of cell counted are low and can give advantages in terms of efficiency, objectivity and time saving in the morphological analysis of blood cells. They can also help in the interpretation of some morphological features and can serve as learning and investigation tools. [ABSTRACT FROM AUTHOR]

To cope with the increasing complexity of digital systems programming, deep learning techniques have recently been proposed to enhance software deployment by analysing source code for different purposes, ranging from performance and energy improvement to debugging and security assessment. As embedded platforms for cyber-physical systems are characterised by increasing heterogeneity and parallelism, one of the most challenging and specific problems is efficiently allocating computational kernels to available hardware resources. In this field, deep learning applied to source code can be a key enabler to face this complexity. However, due to the rapid development of such techniques, it is not easy to understand which of those are suitable and most promising for this class of systems. For this purpose, we discuss recent developments in deep learning for source code analysis, and focus on techniques for kernel mapping on heterogeneous platforms, highlighting recent results, challenges and opportunities for their applications to cyber-physical systems. [ABSTRACT FROM AUTHOR]

Despite its relatively recent history, deep learning (DL)-based source code analysis is already a cornerstone in machine learning for compiler optimization. When applied to the classification of pieces of code to identify the best computational unit in a heterogeneous Systems-on-Chip, it can be effective in supporting decisions that a programmer has otherwise to take manually. Several techniques have been proposed exploiting different networks and input information, prominently sequence-based and graph-based representations, complemented by auxiliary information typically related to payload and device configuration. While the accuracy of DL methods strongly depends on the training and test datasets, so far no exhaustive and statistically meaningful analysis has been done on its impact on the results and on how to effectively extract the available information. This is relevant also considering the scarce availability of source code datasets that can be labeled by profiling on heterogeneous compute units. In this article, we first present such a study, which leads us to devise the contribution of code sequences and auxiliary inputs separately. Starting from this analysis, we then demonstrate that by using the normalization of auxiliary information, it is possible to improve state-of-the-art results in terms of accuracy. Finally, we propose a novel approach exploiting Siamese networks that further improve mapping accuracy by increasing the cardinality of the dataset, thus compensating for its relatively small size. [ABSTRACT FROM AUTHOR]

In their quest toward Exascale, High Performance Computing (HPC) systems are rapidly becoming larger and more complex, together with the issues concerning their maintenance. Luckily, many current HPC systems are endowed with data monitoring infrastructures that characterize the system state, and whose data can be used to train Deep Learning (DL) anomaly detection models, a very popular research area. However, the lack of labels describing the state of the system is a wide-spread issue, as annotating data is a costly task, generally falling on human system administrators and thus does not scale toward exascale. In this article we investigate the possibility to extract labels from a service monitoring tool (Nagios) currently used by HPC system administrators to flag the nodes which undergo maintenance operations. This allows to automatically annotate data collected by a fine-grained monitoring infrastructure; this labelled data is then used to train and validate a DL model for anomaly detection. We conduct the experimental evaluation on a tier-0 production supercomputer hosted at CINECA, Bologna, Italy. The results reveal that the DL model can accurately detect the real failures, and, moreover, it can predict the insurgency of anomalies, by systematically anticipating the actual labels (i.e., the moment when system administrators realize when an anomalous event happened); the average advance time computed on historical traces is around 45 minutes. The proposed technology can be easily scaled toward exascale systems to easy their maintenance. [ABSTRACT FROM AUTHOR]

Objective Some conventional laboratory tests are routinely used for the prediction of systemic autoimmune disease activity, such as the erythrocyte sedimentation rate (ESR) and C-reactive protein (CRP); however, they can give false-negative results, pointing out the need to identify more specific markers. Methods We evaluated biomarkers in 21 Italian patients naïve to treatment with a diagnosis of autoimmune rheumatic disease according to the 2010 American College of Rheumatology/European League Against Rheumatism Classification Criteria for Rheumatoid Arthritis during 6 months of therapeutic treatments. Results We found a significant difference in interleukin-6 (IL-6), CRP, ESR, platelet count, and fecal calprotectin in diagnosed patients compared with healthy participants and a significant decrease in these values during follow-up, except for IL-6 and platelet count. Conclusion We found that CRP, ESR, and fecal calprotectin seemed to be related to autoimmune rheumatic disorders and to be associated with therapy, whereas serum calprotectin and IL-6 did not seem to be associated with disease improvement after the start of treatment, along with leukocyte count and platelet count. [ABSTRACT FROM AUTHOR]

Data centers are increasing in size and complexity, and we need scalable approaches to support their automated analysis and control. Performance counters and power consumption are their key "vital signs". State-of-the-Art (SoA) monitoring systems provide built-in tools to collect performance measurements, and custom solutions to get insight on their power consumption. However, with the increase in measurement resolution (in time and space) and the ensuing huge amount of measurement data to handle, new challenges arise, such as bottlenecks on the network bandwidth, storage and software overhead on the monitoring units. To face these challenges we propose a novel monitoring platform for data centers, which enables real-time high-resolution profiling (i.e., all available performance counters and the entire signal bandwidth of the power consumption at the plug—sampling up to 20 μ s —with an error below 1%) and analytics, both at the edge (node-level analysis) and on a centralized unit (cluster-level analysis). The monitoring infrastructure is completely out-of-band, scalable, technology agnostic and low cost, and it is already installed in a SoA high-performance compute cluster (i.e., D.A.V.I.D.E. —18th in Green500 November 2017). [ABSTRACT FROM AUTHOR]

Summary: Profiling and tuning of parallel applications is an essential part of HPC. Analysis and elimination of application hot spots can be performed using many available tools, which also provides resource consumption measurements for instrumented parts of the code. Since complex applications show different behavior in each part of the code, it is essential to be able to insert instrumentation to analyse these parts. Because each performance analysis or autotuning tool can bring different insights into an application behavior, it is valuable to analyze and optimize an application using a variety of them. We present our on request inserted shared C/C++ API for the most common open‐source HPC performance analysis tools, which simplify the process of the manual instrumentation. Besides manual instrumentation, profiling libraries provide different methods for instrumentation. Of these, the binary patching is the most universal mechanism, and highly improves the user‐friendliness and robustness of the tool. We provide an overview of the most commonly used binary patching tools, and describe a workflow for how to use them to implement a binary instrumentation tool for any profiler or autotuner. We have also evaluated the minimum overhead of the manual and binary instrumentation. [ABSTRACT FROM AUTHOR]

Power and energy consumption are becoming key challenges for the supercomputers’ exascale race. HPC systems’ processors waist active power during communication and synchronization among the MPI processes in large-scale HPC applications. However, due to the time scale at which communication happens, transitioning into low-power states while waiting for the completion of each communication may introduce unacceptable overhead. In this article, we present COUNTDOWN, a run-time library for identifying and automatically reducing the power consumption of the CPUs during communication and synchronization. COUNTDOWN saves energy without penalizing the time-to-completion by lowering CPUs power consumption only during idle times for which power state transition overhead is negligible. This is done transparently to the user, without requiring labor-intensive and error-prone application code modifications, nor requiring recompilation of the application. We test our methodology on a production Tier-1 system. For the NAS benchmarks, COUNTDOWN saves between 6 and 50 percent energy, with a time-to-solution penalty lower than 5 percent. In a complete production—Quantum ESPRESSO—for a 3.5K cores run, COUNTDOWN saves 22.36 percent energy, with a performance penalty below 3 percent. Energy saving increases to 37 percent with a performance penalty of 6.38 percent, if the application is executed without communication tuning. [ABSTRACT FROM AUTHOR]

Power and thermal management are critical components of high-performance-computing (HPC) systems, due to their high-power density and large total power consumption. The assessment of thermal dissipation by means of compact models directly from the thermal response of the final device enables more robust and precise thermal control strategies as well as automated diagnosis. However, when dealing with large-scale systems “in production,” the accuracy of learned thermal models depends on the dynamics of the power excitation, which depends also on the executed workload, and measurement nonidealities such as quantization. In this article we show that, using an advanced system identification algorithm, we are able to generate very accurate thermal models (average error lower than our sensors quantization step of 1 °C) for a large-scale HPC system on real workloads for very long time periods. However, we also show that: 1) not all real workloads allow for the identification of a good model and 2) starting from the theory of system identification it is very difficult to evaluate if a trace of data leads to a good estimated model. We then propose and validate a set of techniques based on machine learning and deep learning algorithms for the choice of data traces to be used for model identification. We also show that deep learning techniques are absolutely necessary to correctly choose such traces up to 96% of the times. [ABSTRACT FROM AUTHOR]

Thermal-aware design and online optimization of the cooling effort are becoming increasingly important in current and future high-performance computing (HPC) systems. A fundamental requirement to effectively develop such techniques is the availability of distributed and compact models representing the system thermal behavior. System identification algorithms allow to extract models directly from the thermal response of the target device. This article proposes a novel thermal identification approach for real, in-production HPC systems, which is capable of extracting thermal models from a computing node affected by quantization noise on the temperature measurements as well as operating in the free-cooling mode, with variable ambient temperature. The approach allows also to identify the physical floorplan of the CPU dies in supercomputing nodes. The effectiveness of the proposed methodology has been tested on a node of the CINECA Galileo Tier-1 supercomputer system. [ABSTRACT FROM AUTHOR]

Energy efficiency is of paramount importance for the sustainability of high performance computing (HPC) systems. Energy consumption limits the peak performance of supercomputers and accounts for a large share of Total Cost of Ownership (TCO). Consequently, system owners and final users have started exploring mechanisms to trade off performance for power consumption, for example, through frequency and voltage scaling. However, only a limited number of studies have been devoted to explore the economic viability of performance scaling solutions and to devise pricing mechanisms fostering a more energy-conscious usage of resources, without adversely impacting return-of-investment on the HPC facility. How to foster green-computing to take advantage of power management knobs? Would today's accounting systems be sufficient or are novel pricing schemes needed? How to model the link between TCO and power management? To answer these questions, we present a parametrized model to analyze the impact of frequency scaling on energy consumption and to assess the potential cost benefits for the HPC facility and users. We evaluate four pricing schemes, considering both facility manager and the user perspectives. We then perform a design space exploration considering current and near-future HPC systems and technologies. [ABSTRACT FROM AUTHOR]

A new pair of optical wireless modems has been realized, which exploit visible light communication to transmit Ethernet signals through water. The modem prototypes were finally tested in sea waters at La Spezia harbor; they successfully transmitted 10 Mbit/s 10Base-T signals over up to 10 m, notwithstanding the high turbidity and the strong sunlight. Final tests included the integration with SUNRISE testbed and the use with a moving robot, remotely operated. Commercial components were used to realize the modems; thus, we expect that the key design concepts can be used as a starting point for practical deployment of this technology. [ABSTRACT FROM AUTHOR]

Supercomputers, nowadays, aggregate a large number of nodes featuring the same nominal HW components (e.g., processors and GPGPUS). In real-life machines, the chips populating each node are subject to a wide range of variability sources, related to performance and temperature operating points (i.e., ACPI p-states) as well as process variations and die binning. Eurora is a fully operational supercomputer prototype that topped July 2013 Green500 and it represents a unique ’living lab’ for next-generation ultra-green supercomputers. In this paper we evaluate and quantify the impact of variability on Eurora's energy-performance tradeoffs under a wide range of workloads intensity. Our experiments demonstrate that variability comes from hardware component mismatches as well as from the interplay between run-time energy management and workload variations. Thus, variability has a significant impact on energy efficiency even at the moderate scale of the Eurora machine, thereby substantiating the critical importance of variability management in future green supercomputers. [ABSTRACT FROM AUTHOR]

Introduction Yeast pathogens are emerging agents of nosocomial as well as community-acquired infections and their rapid and accurate identification is crucial for a better management of high-risk patients and for an adequate treatment. Methods We performed a retrospective review of 156 yeast isolates collected during a 17 months' period of regular clinical practice at the Microbiology Department of San Camillo Hospital in Treviso, Italy and analyzed by the traditional culture-based method combined with matrix-assisted laser desorption ionization-time of flight mass spectrometry (MALDI-TOF MS). Results Out of all the samples collected MALDI-TOF MS was able to characterize with a MT score ≥1.7 (accurate result at species level) 12 different yeast and yeast-like species from 140 samples: Candida albicans (63.7%), Candida glabrata (13.6%), Saccharomyces cerevisiae (6.5%), Candida parapsilosis (5.7%), Candida tropicalis (2.1%), Candida pararugosa (2.1%), Candida guilliermondii (2.1%), Candida kefyr (1.4%), Candida lusitaniae (0.7%), Candida palmioleophila (0.7%), Geotrichum silvicola (0.7%), Rhodotorula mucilaginosa (0.7%). Susceptibility testing toward seven common antifungal agents showed a characteristic MIC distribution of C. albicans isolates for echinocandins: particularly we noticed that 72% and 46% of C. albicans showed an MIC value close to clinical breakpoint as defined by EUCAST, respectively for anidulafungin and micafungin. Conclusion Accurate identification of microorganisms and the study of their antifungal susceptibility allow to understand the epidemiology of a particular area, permitting the choice of the most appropriate early antifungal treatment. [ABSTRACT FROM AUTHOR]

In recent years, compressed sensing (CS) has proved to be effective in lowering the power consumption of sensing nodes in biomedical signal processing devices. This is due to the fact the CS is capable of reducing the amount of data to be transmitted to ensure correct reconstruction of the acquired waveforms. Rakeness-based CS has been introduced to further reduce the amount of transmitted data by exploiting the uneven distribution to the sensed signal energy. Yet, so far no thorough analysis exists on the impact of its adoption on CS decoder performance. The latter point is of great importance, since body-area sensor network architectures may include intermediate gateway nodes that receive and reconstruct signals to provide local services before relaying data to a remote server. In this paper, we fill this gap by showing that rakeness-based design also improves reconstruction performance. We quantify these findings in the case of ECG signals and when a variety of reconstruction algorithms are used either in a low-power microcontroller or a heterogeneous mobile computing platform. [ABSTRACT FROM PUBLISHER]

With CMOS scaling beyond 14 nm, reliability is a major concern for IC manufacturers. Reliability-aware design has a non-negligible overhead and cannot account for user experience in mobile devices. An alternative is dynamic reliability management (DRM), which counteracts degradation by adapting the operating conditions at runtime. In this paper, for the first time we formulate DRM as an optimization problem that accounts for reliability, temperature and performance. We develop an optimal policy for multicores using convex optimization, and show that it is not feasible to implement on real systems. For this reason, we propose workload-aware reliability management (WARM), a fast DRM technique adapting to diverse workload requirements to trade reliability and user experience. WARM is implemented and tested on a real Android device. WARM approximates the solution of the convex solver within 5% on average, while executing more than 400 \times faster. WARM integrates a thermal controller that allocates tasks to meet thermal constraints. This is required since degradation strongly depends on temperature. We show that WARM meets temperature constraints within 5% in 87.5% more cases than the state-of-the-art. We show that WARM task allocation achieves up to one year lifetime improvement for a multicore platform. It can achieve up to 100% of performance improvement on cluster architectures, such as big.LITTLE, while still guaranteeing the reliability target. Finally, we show that it achieves performance in the 4% of the maximum for a broad range of a applications, while meeting the reliability constraints. [ABSTRACT FROM PUBLISHER]

Ultrasound imaging is a reference medical diagnostic technique, thanks to its blend of versatility, effectiveness, and moderate cost. The core computation of all ultrasound imaging methods is based on simple formulae, except for those required to calculate acoustic propagation delays with high precision and throughput. Unfortunately, advanced three-dimensional (3-D) systems require the calculation or storage of billions of such delay values per frame, which is a challenge. In 2-D systems, this requirement can be four orders of magnitude lower, but efficient computation is still crucial in view of low-power implementations that can be battery-operated, enabling usage in numerous additional scenarios. In this paper, we explore two smart designs of the delay generation function. To quantify their hardware cost, we implement them on FPGA and study their footprint and performance. We evaluate how these architectures scale to different ultrasound applications, from a low-power 2-D system to a next-generation 3-D machine. When using numerical approximations, we demonstrate the ability to generate delay values with sufficient throughput to support 10 000-channel 3-D imaging at up to 30 fps while using 63% of a Virtex 7 FPGA, requiring 24 MB of external memory accessed at about 32 GB/s bandwidth. Alternatively, with similar FPGA occupation, we show an exact calculation method that reaches 24 fps on 1225-channel 3-D imaging and does not require external memory at all. Both designs can be scaled to use a negligible amount of resources for 2-D imaging in low-power applications and for ultrafast 2-D imaging at hundreds of frames per second. [ABSTRACT FROM PUBLISHER]

In the last decade, improvements on technology scaling have enabled the design of a novel generation of wearable bio-sensing monitors. These smart Wireless Body Sensor Nodes (WBSNs) are able to acquire and process biological signals, such as electrocardiograms, for periods of time extending from hours to days. The energy required for the on-node digital signal processing (DSP) is a crucial limiting factor in the conception of these devices. To address this design challenge, we introduce a domain-specific ultra-low power (ULP) architecture dedicated to bio-signal processing. The platform features a light-weight strategy to support different operating modes and synchronization among cores. Our approach effectively reduces the power consumption, harnessing the intrinsic parallelism and the workload requirements characterizing the target domain. Operations at low voltage levels are supported by a heterogeneous memory subsystem comprising a standard-cell based ultra-low voltage reliable partition. Experimental results show that, when executing real-world bio-signal DSP applications, a state-of-the-art multi-core architecture can improve its energy efficiency in up to 50 percent by utilizing our proposed approach, outperforming traditional single-core alternatives. [ABSTRACT FROM PUBLISHER]