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The use of sunscreens is recommended to limit the impact of sun exposure on the skin. The objective of this study was to examine the relationship between sunscreen sales and melanoma in 4 different countries with diverse sunscreen regulations. Data from publicly available databases were examined for Sweden, England, Australia, and the USA from 1999 to 2018. The association between incidence of melanoma and sunscreen sales was estimated using a generalized estimating equation, and modelling was used to predict melanoma cases. Incidence of melanoma was positively associated with sunscreen sales in England, Australia, and the USA, and negatively associated with sunscreen sales in Sweden. Growth rates in melanoma cases of 0.42%, 16.7%, 19.1% and 12.2% were predicted for Sweden, England, Australia, and the USA, respectively. The differences observed between England, Australia, and the USA, on the one hand, and Sweden, on the other hand, are consistent with the adoption of strong regulations requiring the use of ultraviolet A blocking agents in sunscreens. [ABSTRACT FROM AUTHOR]

As nanometer technology advances, conventional optical proximity correction (OPC) that minimizes the edge placement error (EPE) at the nominal process condition alone often leads to poor process windows. To improve the mask printability across various process corners, process-window OPC optimizes EPE for multiple process corners, but often suffers long runtime, due to repeated lithographic simulations. This paper presents an efficient process variation (PV)-aware mask optimization framework, namely PVOPC, to simultaneously minimize EPE and PV band with fast convergence. The PVOPC framework includes EPE-sensitivity-driven dynamic fragmentation, PV-aware EPE modeling, and correction with three new EPE-converging techniques and a systematic subresolution-assisted feature insertion algorithm. Experimental results show that our approach efficiently achieves high-quality EPE and PV band results. [ABSTRACT FROM AUTHOR]

Low-k1 lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower-level metals used for local routing, where bi-directionality and tight pitches give rise to lithography unfriendly layout patterns. However, there exists inherent unutilized flexibility in design shapes, e.g., one can modify such wires without significantly affecting design behavior. We develop two different techniques to simultaneously modify mask and design shapes during optical proximity correction (OPC) to improve lithographic yield of low-level metal layers. The methods utilize image slope information, which is available during OPC image simulations at no extra cost, as a measure of lithographic process window. We first propose a method that identifies fragments with low normalized image log slope (NILS) and then use this NILS information to guide dynamic target modification between iterations of OPC. The method uses a pre-characterized lookup table to assign a different magnitude of local target correction to different NILS bins. Next we develop an optimization flow where we derive a cost function that maximizes both contour fidelity and robustness to drive our simultaneous mask and target optimization (SMATO) method. We develop analytical equations to predict the cost for a given mask and target modification and use a fast algorithm to minimize this cost function to obtain an optimal mask and target solution. Our experiments on sample 1 x (M1) layouts show that the use of SMATO reduces the process manufacturability index (PMI) by 15.4% compared with OPC, which further leads to 69% reduction in the number of layout hotspots. Additionally, such improvement is obtained at low average runtime overhead (5.5%). Compared with process window optical proximity correction (PWOPC), we observe 4.6% improvement in PMI at large (2.6x) improvement in runtime. [ABSTRACT FROM AUTHOR]

The move to low-k1 lithography makes it increasingly difficult to print feature sizes that are a small fraction of the wavelength of light. With further delay in the delivery of extreme ultraviolet lithography, these difficulties will motivate the research community to explore increasingly broad solutions. We propose that there is significant research potential in studying the essential premise of the design/manufacturing handoff paradigm. Today this premise revolves around design rules that define what implementations are legal, and raw shapes, which define design intent, and are treated as a fixed requirement for lithography. In reality, layout features may vary within certain tolerances without violating any design constraints. The knowledge of such tolerances can help improve the manufacturability of layout features while still meeting design requirements. We propose a methodology to convert electrical slack in a design to shape slack or tolerances on individual layout shapes. We show how this can be done for two important implementation fabrics: (a) cell-library-based digital logic and (b) static random access memory. We further develop a tolerance-driven optical proximity correction algorithm that utilizes this shape slack information during mask preparation to ensure that all features prints within their shape slacks in presence of lithographic process variations. Experiments on 45 nm silicon on insulator cells using accurate process models show that this approach reduces postlithography delay errors by 50%, and layout hotspots by 47% compared to conventional methods. [ABSTRACT FROM AUTHOR]