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In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage. [ABSTRACT FROM PUBLISHER]

This paper shows the potential benefits of using the trigate junctionless transistor (JLT) with dual- k sidewall spacers to enhance analog/radio-frequency (RF) performance at 20-nm gate length. Simulation study shows that the source-side-only dual- k spacer (dual- kS) JLT can improve all analog/RF figures of merit (FOMs) compared with the conventional JLT structure. The dual- kS JLT shows improvement in intrinsic voltage gain ( $$A_{V0}$$ ) by $$\sim $$ 44.58 %, unity-gain cutoff frequency ( $$f_\mathrm{T}$$ ) by $$\sim $$ 7.67 %, and maximum oscillation frequency ( $$f_\mathrm{MAX}$$ ) by $$\sim $$ 6.4 % at drain current $$(I_\mathrm{ds}) = 10\,\upmu \hbox {A}/\upmu \hbox {m}$$ compared with the conventional JLT structure. To justify the improvement in all analog/RF FOMs, it is also found that the dual- kS structure shows high electron velocity near the source region because of the presence of an additional electric field peak near the source region, resulting in increased electron transport efficiency and hence improved transconductance ( $$g_\mathrm{m}$$ ). Furthermore, the dual- kS JLT shows a reduction in the electric field value near the drain end, thereby improving short-channel effects. [ABSTRACT FROM AUTHOR]

Compact models for MOS devices are extremely useful as they can be incorporated in circuit simulators with sufficient accuracy. We present for the first time a 2-D surface-potential-based compact model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixed-oxide charge densities at both front- and back-gates. The proposed drain current model is accurate, computationally efficient, and suitable for circuit simulation in the nanometer regime because no iterative loop is used anywhere. The drain current model includes velocity saturation, channel length modulation, carrier mobility degradation, and also the drain-induced barrier lowering. The model shows excellent concordance with the reported experimental transfer characteristic curves for both the high and low drain voltages and also exhibits good agreement for derivatives of drain current when compared with our TCAD simulation data for GeOI devices with channel length of 30 nm over a wide range of gate and drain bias conditions. Furthermore, our studies reveal that GeOI devices outperform silicon-on-insulator (SOI) counterparts in terms of analog figures of merit, such as transconductance, voltage gain, transconductance generation factor, and cut-off frequency, except the output conductance. [ABSTRACT FROM AUTHOR]