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This paper presents a novel, compact, and energy-efficient hysteretic boost converter that employs an anti-phase AC-coupling emulate current control. The proposed scheme utilizes a two-transistor current emulator and a comparator, which allow for fast transient responses and tight closed-loop regulations. This converter was fabricated using a 180 nm CMOS process and was capable of regulating a 5 V output with a 400 mA load capacity from an input voltage range of 2.7 V to 4.5 V. The experimental results demonstrate that the proposed anti-phase AC-coupling emulate current controlling and single hysteretic comparator controlling scheme show lower power/circuit complexity and better static and transient performance. Specifically, under load transitions ranging from 0 mA to 300 mA, the converter exhibits over/undershoot voltages of 38 mV and −42 mV, respectively. Furthermore, the measured load and line regulation performances are 5 mV/A and 2.3 mV/V, respectively. Overall, this study offers a practical and efficient solution for boosting voltage levels while maintaining stable and precise regulation. [ABSTRACT FROM AUTHOR]

This proposed work introduces a DC-DC converter with Switched-Capacitor Delay Deadtime Controller (SCD-DTC), Digitally Controlled Start-Up Block (DC-SUB), and Enhanced Unbalanced-Input Pair Zero-Current Detector (EUIP-ZCD) that helps to improve the overall power efficiency. It also introduces the discussion of key signal waveforms and the two major optimization flowcharts. This proposed DC-DC converter can simultaneously achieve optimized deadtime (body diode conduction < 3 ns) and almost fully eliminate the phenomenon of reverse inductor current (RIC). Furthermore, it also shows that it can achieve a well-regulated output voltage of 1.8 V with <0.01% of output ripple riding on it. All the post-layout simulation results are carried out using 0.18 µm 1P6M CMOS process using Cadence Virtuoso Spectre Circuit Simulator. The silicon chip area of our proposed work (including the output pad frame) is 1.44 mm2. The chip fabrication was sent out in January 2024 and the return of the measurement dies is expected in March 2024. The post-layout simulation results will no doubt closely resemble the measurement results since the proposed work is mostly controlled by digital blocks. [ABSTRACT FROM AUTHOR]

In this paper, the effects of proton and gamma irradiation on reach-through single-photon avalanche diodes (SPADs) are investigated. The I–V characteristics, gain and spectral response of SPAD devices under proton and gamma irradiation were measured at different proton energies and irradiation bias conditions. Comparison experiments of proton and gamma irradiation were performed in the radiation environment of geosynchronous transfer orbit (GTO) with two different radiation shielding designs at the same total ionizing dose (TID). The results show that after 30 MeV and 60 MeV proton irradiation, the leakage current and gain increase, while the spectral response decreases slightly. The leakage current degradation is more severe under the "ON"-bias condition compared to the "OFF"-bias condition, and it is more sensitive to the displacement radiation damage caused by protons compared to gamma rays under the same TID. Further analysis reveals that the non-elastic and elastic cross-section of protons in silicon is 1.05 × 105 times greater than that of gamma rays. This results in SPAD devices being more sensitive to displacement radiation damage than ionizing radiation damage. Under the designed shielding conditions, the leakage current, gain and spectral response parameters of SPADs do not show significant performance degradation in the orbit. [ABSTRACT FROM AUTHOR]

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 108 MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO2 interface trap generated by ionization. [ABSTRACT FROM AUTHOR]

Renewable energy sources play a pivotal role in the pursuit of sustainable and eco-friendly power solutions. While offering environmental benefits, they present inherent challenges. Photovoltaic systems rely on surrounding conditions, wind systems contend with variable wind speeds, and fuel cells are both costly and inefficient. Furthermore, the energy injected by renewable energy sources (RES) exhibits unpredictable behavior. To tackle these problems, researchers employ diverse power electronic devices and converters like inverters, power quality filters, and DC–DC choppers. Among these, DC–DC converters stand out for effectively regulating DC voltage and enhancing the efficiency of RESs. The meticulous selection of a suitable DC–DC converter, coupled with the integration of an efficient control technique, significantly influences overall power system performance. This paper introduces a novel approach to the design of switching controllers for DC–DC converters, specifically tailored for application in renewable energy systems. The proposed controller leverages the power of composite switched Lyapunov functions (CSLF) to enhance the efficiency and performance of DC–DC converters, addressing the unique challenges posed by renewable energy sources. Through comprehensive analysis and simulation, this study demonstrates the efficacy of the controller in optimizing power transfer, improving stability, and ensuring reliable operation in diverse renewable energy environments. Moreover, the small-scale DC–DC converter experiment's findings are presented to confirm and validate the proposed scheme's practical applicability. [ABSTRACT FROM AUTHOR]

Using a single photon avalanche diode (SPAD) as a receiver in an optical wireless communications (OWC) system can effectively expand the transmission distance. However, the performance of the SPAD receiver is usually affected with the bit error rate (BER) lower bound determined by background light and the inter-symbol interference (ISI) distortion caused by dead time. In this paper, external time-gated technology is employed, and the SPAD is only activated within the set gate-ON time to alleviate the influence of background light and ISI distortion. The SPAD photon counting model and the communication BER model are established according to the external time-gated characteristics. Considering the functional relationship among the gate-ON time, signal light flux, background light flux and blocking time, we take the minimum BER as the optimization target, the optimal gate-ON time is derived. The numerical results show that whenever the signal light flux or the background light flux is higher, the BER performance of the time-gated mode is apparently better than the free-running mode. For example, when signal photons and background photons are 30 and 10 per symbol time, respectively, the BER of free-running SPAD converges to 0.1, while the BER of the time-gated scheme is about 10 − 6 . [ABSTRACT FROM AUTHOR]

Silicon Photomultipliers (SiPMs) are photo-electronic devices able to detect single photons and permit the measurement of weak optical signals. Single-photon detection is accomplished through high-performance read-out front-end electronics whose design needs accurate modeling of the photomultiplier device. In the past, a useful model was developed, but it is limited to the device electrical characteristic and its parameter extraction procedure requires several measurement steps. A new silicon photomultiplier model is proposed in this paper. It exploits the Verilog-a behavioral language and is appropriate to transistor-level circuit simulations. The photon detection of a single cell is modeled using the traditional electrical model. A statistical model is included to describe the silicon photomultiplier noise caused by dark-count or after-pulsing effects. The paper also includes a procedure for the extraction of the model parameters through measurements. The Verilog-a model and the extraction procedure are validated by comparing simulations to experimental results. [ABSTRACT FROM AUTHOR]

The 8-channel Multiple Use Silicon Photo-multiplier (SiPM) Integrated Circuit (MUSIC) Application specific integrated circuit (ASIC) for SiPM anode readout has been designed for applications where large photo-detection areas are required. MUSIC offers three main features: (1) Sum of the eight input channels using a differential output driver, (2) eight individual single ended (SE) analog outputs, and (3) eight individual SE binary outputs using a time over threshold technique. Each functionality, summation and individual readout includes a selectable dual-gain configuration. Moreover, the signal sum implements a dual-gain output providing a 15-bit dynamic range. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with most of the available SiPM devices in the market. Experimental tests show how MUSIC can linearly sum signals from different SiPMs and distinguish even a few photons. Additionally, it provides a single photon output pulse width at half maximum (FWHM) between 5–10 ns for the analog output and a single-photon time resolution (SPTR) around 118 ps sigma using a Hamamatsu SiPM S13360-3075CS for the binary output. Lastly, the summation mode has a power consumption of ≈200 mW, whereas the individual readout consumes ≈30 mW/ch. [ABSTRACT FROM AUTHOR]

This paper presents a 20-channel coincidence counting unit (CCU) using a low-end field-programmable gate array (FPGA). The architecture of the CCU can be configured arbitrarily to measure from twofold to twentyfold coincidence counts thanks to a multifold controllable architecture, which can be easily manipulated by a graphical user interface (GUI) program. In addition, it provides up to 20 of each input signal count simultaneously. The experimental results show twentyfold coincidence counts with the resolution occurring in a less than 0.5 ns coincidence window. This CCU has appropriate characteristics for various quantum optics experiments using multi-photon qubits. [ABSTRACT FROM AUTHOR]

The design and implementation of a real-time breakdown voltage and on-chip temperature monitoring system for single photon avalanche diodes (SPADs) is described in this work. In the system, an on-chip shaded (active area of the detector covered by a metal layer) SPAD is used to provide a dark count rate for the breakdown voltage and temperature calculation. A bias circuit was designed to provide a bias voltage scanning for the shaded SPAD. A microcontroller records the pulses from the anode of the shaded SPAD and calculates its real-time dark count rate. An algorithm was developed for the microcontroller to calculate the SPAD's breakdown voltage and the on-chip temperature in real time. Experimental results show that the system is capable of measuring the SPAD's breakdown voltage with a mismatch of less than 1.2%. Results also show that the system can provide real-time on-chip temperature monitoring for the range of −10 to 50 °C with errors of less than 1.7 °C. The system proposed can be used for the real-time SPAD's breakdown voltage and temperature estimation for dual-SPADs or SPAD arrays chip where identical detectors are fabricated on the same chip and one or more dummy SPADs are shaded. With the breakdown voltage and the on-chip temperature monitoring, intelligent control logic can be developed to optimize the performance of the SPAD-based photon counting system by adjusting the parameters such as excess bias voltage and dead-time. This is particularly useful for SPAD photon counting systems used in complex working environments such as the applications in 3D LIDAR imaging for geodesy, geology, geomorphology, forestry, atmospheric physics and autonomous vehicles. [ABSTRACT FROM AUTHOR]

A compact single-photon counting module that can accurately control the bias voltage and hold-off time is developed in this work. The module is a microcontroller-based system which mainly consists of a microcontroller, a programmable negative voltage generator, a silicon-based single-photon avalanche diode, and an integrated active quench and reset circuit. The module is 3.8 cm × 3.6 cm × 2 cm in size and can communicate with the end user and be powered through a USB cable (5 V). In this module, the bias voltage of the single-photon avalanche diode (SPAD) is precisely controllable from −14 V ~ −38 V and the hold-off time (consequently the dead time) of the SPAD can be adjusted from a few nanoseconds to around 1.6 μs with a setting resolution of ∼6.5 ns. Experimental results show that the module achieves a minimum dead time of around 28.5 ns, giving a saturation counting rate of around 35 Mcounts/s. Results also show that at a controlled reverse bias voltage of 26.8 V, the dark count rate measured is about 300 counts/s and the timing jitter measured is about 158 ps. Photodetection probability measurements show that the module is suited for detection of visible light from 450 nm to 800 nm with a 40% peak photon detection efficiency achieved at around 600 nm. [ABSTRACT FROM AUTHOR]