Search

This paper proposes an optimized hardware implementation method for existing CIE1931 color gamut control algorithm. Among the post-processing methods of dehazing algorithms, existing algorithm with relatively low computations have the disadvantage of consuming many hardware resources by calculating large bits using Split multiplier in the computation process. The proposed algorithm achieves computational reduction and hardware miniaturization by reducing the predefined two matrix multiplication operations of the existing algorithm to one. And by optimizing the Split multiplier computation, it is implemented more efficient hardware to mount. The hardware was designed in the Verilog HDL language, and the results of logical synthesis using the Xilinx Vivado program were compared to verify real-time processing performance in 4K environments. Furthermore, this paper verifies the performance of the proposed hardware with mounting results on two FPGAs. [ABSTRACT FROM AUTHOR]

Bluetooth is a common wireless technology that is widely used as a connection medium between various consumer electronic devices. The Bluetooth receiver usually adopts a Viterbi algorithm to improve signal-to-noise ratio performance, but requires complex hardware and calculations for continuous search and estimation for the irrational modulation indexes at the transmission. This paper proposes a non-coherent maximum estimation based 8-State Viterbi FSM to solve these complexity problems. The proposed optimal Viterbi FSM can detect Gaussian frequency-shfit keying symbol without any prior information and estimation for the modulation indexes. The HV1/HV2 packets are used for the estimation of the proposed algorithm and the simulation results have shown performance improvements with about 2dB for 10 -3 BER compared to other ideal approaches such as decision direct method. [ABSTRACT FROM AUTHOR]

As technologies related to image processing such as autonomous driving and CCTV develop, fog removal algorithms using a single image are being studied to improve the problem of image distortion. As a method of predicting fog density, there is a method of estimating the depth of an image by generating a depth map, and various fog features may be used as training data of the depth map. In addition, it is essential to implement a hardware capable of processing high-definition images in real time in order to apply the fog removal algorithm to actual technologies. In this paper, we implement NLCV (Normalize Local Coefficient of Variation), a feature of fog based on coefficient of variation, in hardware. The proposed hardware is an FPGA implementation of Xilinx's xczu7ev-2ffvc1156 as a target device. As a result of synthesis through the Vivado program, it has a maximum operating frequency of 479.616MHz and shows that real-time processing is possible in 4K UHD environment. [ABSTRACT FROM AUTHOR]

The paradigm of Internet-of-things(IoT) systems is changing from a cloud-based system to an edge-based system to solve delays caused by network congestion, server overload and security issues due to data transmission. However, edge-based IoT systems have fatal weaknesses such as lack of performance and flexibility due to various limitations. To improve performance, application-specific hardware can be implemented in the edge device, but performance cannot be improved except for specific applications due to a fixed function. This paper introduces a edge-centric metamorphic IoT(mIoT) platform that can use a variety of hardware through on-demand partial reconfiguration despite the limited hardware resources of the edge device, so we can increase the performance and flexibility of the edge device. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to previous studies in which the reconfiguration algorithm was executed on the server. [ABSTRACT FROM AUTHOR]

This paper presents a low cost hardware message passing engine of enhanced atomic pipelined broadcast based on processing node status. In this algorithm, the previous atomic pipelined broadcast algorithm is modified to reduce the waiting time until next broadcast communication. For this, the processor change the transmission order of processing nodes based on the nodes’ communication channel. Also, the hardware message passing engine architecture of the proposed algorithm is modified to be adopted to multi-core processor. The synthesized logic area of the proposed hardware message passing engine was reduced by about 16%, compared by the pre-existing hardware message passing engine. [ABSTRACT FROM AUTHOR]

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a 0.18㎛ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency. [ABSTRACT FROM AUTHOR]