Search

In advanced IC manufacturing, as the gap between lithography optical wavelength and feature size increases, it becomes challenging to detect problematic layout patterns called lithography hotspot. In this paper, we propose a novel fuzzy matching model which can dynamically tune appropriate fuzzy regions around known hotspots. Based on this model, we develop a fast algorithm for lithography hotspot detection with very low chances of false-alarm. Our results are very encouraging with under 0.56 CPU-hrs/mm2 runtime. [ABSTRACT FROM AUTHOR]

Within the past decade, mobile computing has morphed into a principal form of human communication, business, and social interaction. Unfortunately, the energy demands of newer ambient intelligence and collaborative technologies on mobile devices have greatly overwhelmed modern energy storage abilities. This paper proposes several novel techniques that exploit spatiotemporal and device context to predict device interface configurations that can optimize energy consumption in mobile embedded systems. These techniques, which include variants of linear discriminant analysis, linear logistic regression, non-linear logistic regression with neural networks, and k-nearest neighbor are explored and compared on synthetic and user traces from real-world usage studies. The experimental results show that up to 90% successful prediction is possible with neural networks and k-nearest neighbor algorithms, improving upon prediction strategies in prior work by approximately 50%. Further, an average improvement of 24% energy savings is achieved compared to state-of-the-art prior work on energy-efficient location-sensing. [ABSTRACT FROM AUTHOR]

As lithography process nodes shrink to sub-wavelength levels generating acceptable layout patterns becomes a challenging problem. Traditionally, complex convolution based lithography simulations are used to estimate areas of high variability. These methods are slow and infeasible for large scale full chip analysis. This work proposes a solution to this problem by using machine learning techniques to identify layout areas that are more prone to variability. A novel target layout representation is proposed, and the latest support vector machine (SVM) algorithms are used to detect variability within standard cells and between cells in a simulated full chip layout. [ABSTRACT FROM AUTHOR]