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Logarithmic sensors are capable of capturing the wide dynamic range of intensities available in nature with minimum number of bits and post-processing required. A simple circuit able to perform logarithmic capture is one utilising a MOS device in weak inversion. However, the output of this pixel is crippled due to fixed pattern noise. Technique proposed to reduce this noise fail to produce high quality images on account of unaccounted high gain variations in the pixel. An electronic calibration technique is proposed which is capable of reducing both multiplicative as well as additive FPN. Contrast properties matching that of human eye are reported from these sensors. With reduced FPN, the pixel performance at low intensities becomes concerning. In these regions, the high leakage current of the CMOS process affects the logarithmic pixel. To reduce this current, two different techniques using a modified circuit and another with modified layout are tested. The layout technique is observed to reduce the leakage current. In addition, this layout can be used to linearise the output of logarithmic pixel in low light regions. The unique linear response at low light and logarithmic pixel at high light is further investigated. A new model based on the device physics is derived to represent this response. The fixed pattern noise profile is also investigated. An intelligent iterative scheme is proposed and verified to extract the photocurrent flowing in the pixel and correct the fixed pattern noise utilising the new model. Future research ideas leading to better designs of logarithmic pixels and post-processing of these signals are proposed at the end of the thesis.

The research discussed here aims to design a deep learning algorithm based on Convolutional Neural Networks models to detect driver distraction and fatigue using driver facial expressions. The proposed model provides high accuracy during both training and validation. The research was inspired to contribute to transport safety by providing alternative solutions to detect driver habit. First, the thesis discussed Conventional methods, including Haar cascade classifiers and eigenfaces. In 2018 I published a proposal for a blink rate detection system using Haar cascade feature detection. However, due to the advantages of Neural Networks, the research focused on providing a unique solution in that field. An in-depth look at how Neural Networks function, specifically Convolutional Neural Networks (CNNs), was investigated and discussed next. Due to the advantages CNN's have with feature detection in images, the algorithm I proposed in this research uses a CNN architecture. Lastly, I proposed an adaptive approach for deep learning to enhance training, validation and testing accuracies. My original algorithm and subsequent models were trained on two datasets. These were the American University in Cairo (AUC) Distracted Driver Dataset and the UTA Real-Life Drowsiness Dataset (UTA-RLDD). Hence the research proposed two original CNN models that produced high training and validation accuracy. The model designed on the AUC Distracted Driver Dataset achieved good 97% training accuracy and good 96% validation accuracy. Evaluation of this model produced good 99% accuracy. The model designed on UTA-RLDD achieved 100% training accuracy, 69% validation accuracy, and evaluated at 69% accuracy.

Nonlinear dynamics is a field that has been widely studied by mathematicians and scientists. However, engineers are yet to exploit the full potential of nonlinearity in coupled systems despite the majority of real physical systems being inherently nonlinear. Although a vast array of results has been generated from simulations, only a small number of physical systems have been investigated. In a 1955 report, Fermi, Pasta, Ulam, and Tsingou reported recurrence of energy between modes in a simple mass-spring system containing a nonlinear coupling term. Extensive numerical simulations of the FPUT system have followed this discovery. However, minimal evidence of FPUT recurrence has been observed in physical systems. This may be due to the effect of 'real-world' imperfections on the ideal systems used in the simulations. Variations between system components due to manufacturing tolerances and energy losses through damping are present in most physical systems. By understanding the effects of these imperfections, it may be possible to apply the results of the simulations to physical systems. The effects of tolerance and damping on recurrence were studied using a series of simulations. The results demonstrate that such imperfections degrade the observation of recurrence, often leading to complete loss in moderately sized arrays. These simulations enabled the identification of a series of conditions under which a practical system might display recurrence. Tight tolerances, low damping, small array size and moderately weak coupling strengths are required. An electronic amplifier circuit was designed to meet these constraints. Preliminary testing of this electronic system has provided early verification of the simulation results. FPUT recurrence was observed a system with four elements. These results suggest that without considering tolerances in real systems, the applicability of the results from simulations to physical systems may be limited.

This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few remaining speed bottlenecks in conventional 2D imagers. At the same time, as pixel dark current continues to improve, the resolution requirements on imaging data converters impose very high system-level design challenges. The focus of the presented investigations here is to shed light on methods in Time-to-Digital Converter interpolation of single-slope ADCs. By using high-factor time-interpolation, the resolution of single-slope converters can be increased without sacrificing conversion time or power. This work emphasizes on solutions for improvement of multiphase clock interpolation schemes, following an all-digital design paradigm. Presented is a digital calibration scheme which allows a complete elimination of analog clock generation blocks, such as PLL or DLL in Flash TDC-interpolated single-slope converters. To match the multiphase clocks in time-interpolated single-slope ADCs, the latter are generated by a conventional open-loop delay line. In order to correct the process voltage and temperature drift of the delay line, a digital backend calibration has been developed. It is also executed online, in-column, and at the end of each sample conversion. The introduced concept has been tested in silicon, and has showed promising results for its introduction in practical mass-production scenarios. Methods for reference voltage generation in single-slope ADCs have also been looked at. The origins of error and noise phenomenona, which occur during both the discrete and continuous-time conversion phases in a single-slope ADC have been mathematically formalized. A method for practical measurement of noise on the ramp reference voltage has also been presented. Multiphase clock interpolation schemes are difficult for implementation when high interpolation factors are used, due to their quadratic clock phase growth with resolution. To allow high interpolation factors a time-domain binary search concept with error calibration has been introduced. Although the study being conceptual, it shows promising results for highly efficient implementations, if a solution to stable column-level unit delays can be found. The latter is listed as a matter of future investigations.

Complementary Metal Oxide Semiconductor (CMOS) image sensors are widely used in many applications such as consumer electronics, automotive and security. One of the key requirements in today's imaging applications is the ability to capture natural scenes faithfully; a feature known as wide dynamic range (WDR). Current digital image sensors have a linear response that results in saturation and loss of details. Conventional CMOS image sensors with a logarithmic response attempt to address the limited dynamic range of the linear digital image sensors by exploiting the subthreshold operation of a transistor in a pixel. This results in CMOS pixels that are able to capture light intensities of more than six decades (120 dB). However, the approach comes at the expense of high fixed pattern noise (FPN) and slow response. The work presented in this thesis describes a five all nMOS transistor (5T) pixel architecture that aims to achieve wide dynamic range. This feature is obtained using a time-varying reference voltage that is applied to one of the transistors of the pixel. The reference voltage varies in a logarithmic fashion in order to modulate the effective integration time of the pixel. This allows the pixel to avoid saturation; hence extending the dynamic range. In addition, the slope of the reference voltage that can be adjusted means the pixel response is adaptive and can be more robust towards temporal noise. To have a well-controlled pixel response, the pixel non-ideal effects such as source follower gain, body effect and subthreshold effect are characterised and included as an improved model to the reference voltage. Measurement results from fabricated chips using UMC 180 nm technology are presented and analysed. A dynamic range of 80 dB with a logarithmic response of 600 mV/decade has been achieved. This is a significant improvement in comparison to that of conventional logarithmic pixel response (60 mV/decade). An analysis of the effect of chip variations that causes FPN has been conducted and correction methods that can reduce the illumination error to less than 2% have been proposed. In addition, the first experimental study comparing different dynamic range extension methods has been performed. In the study, a method to control the response of a WDR approach using a stepped voltage that has achieved a dynamic range of up to 120 dB is also presented. The result of the study leads to a modification to the reference voltage that allows an implementation of an analogue circuit to generate the reference voltage.

With advances in nanotechnology, resonant sensors based on micro/nano electromechanical systems (M/NEMS) have been manufactured utilising a process similar to that of microelectronics. By providing a frequency shift proportional to the mass/stiffness change, these small resonators enable rapid detection of extremely minute changes in mass and force. For example, they can be used to trace the concentration of pathogens. M/NEMS resonators also demonstrate excellent compatibility with electronic circuits, hence offering multi-function and single-chip solutions for next-generation sensing applications. Resonators are coupled to provide extra degrees of freedom for multi-sensing, while reducing a majority of connections required. The collective behaviour of coupled systems gives rise to new sensing methods such as eigenvalue and eigenvector sensing, which exhibit enhanced sensitivity and linearity as opposed to the traditional frequency-shift approach. However, the mechanisms of coupling have not yet been fully exploited. Coupled micro/nano systems are exposed to several challenges. First, process variability is known to degrade sensor performance. Moreover, the readout and signal processing issues in large arrays have not been addressed. Hence, actuating and testing coupled sensors are expensive and time-consuming. These hurdles can be circumvented using a novel inverse eigenvalue analysis (IEA) method proposed in this thesis, which is capable of characterising coupled systems based on inverse and forward analysis. The method extracts the system matrix, which carries deterministic information about process and sensitivity, by attaching a peripheral electrical resonator to the MEMS array, therefore providing the advantages of simplified actuation, accurate calibration and sensitivity trimming. To explore the ultimate limit of scaling, prototype sensors consisting of different numbers of coupled resonators have been designed, fabricated and tested for sensing. By investigating the unique behaviour of eigenvalues, various approaches have been proposed to enhance the accuracy of inverse eigenvalue sensing in large coupled systems.

Complementary Metal-Oxide Semiconductor (CMOS) image sensors are the principal technology employed in commercial image sensing applications. The research interest in these devices is driven by the high demand of cameras. High-quality imagers are relevant in the mobile devices business and are even more important in the automotive market segment where the image quality is crucial for safety. However, CMOS image sensors performance can still be improved. In particular, a leakage current, intrinsic to the process of manufacturing CMOS technology, reduces the sensitivity in low light and should be minimised. In addition, the capability of the sensor to collect electrons, known as full well capacity, should be maximised. The methods proposed in the literature to reduce the leakage current and to increase the full well capacity are either insufficient or costly as they may require process modifications. To overcome these limitations, a different approach based on simple layout modifications is proposed. The principal source of leakage current is due to the photodiode isolation. By designing pixels adjacently, the isolation can be removed thereby reducing the leakage current contribution. In order to maximise the full well capacity, a novel technique is proposed here which consist in minimising the area reserved to the transistors in the pixel array by sharing the maximum number of diffusions. The result is a pixel with a 50% increase in fill factor compared to a traditional pixel. The proposed optimisation strategy results in a staggered pixel arrangement. This may introduce artefacts in the image when displayed. Hardware-efficient image reconstruction algorithms able to correct the artefacts are presented. Test chips were manufactured to prove the performance improvement and experimental data showed that the proposed layouts effectively reduces the leakage current and improved the full well capacity of the presented pixels. In addition, the proposed algorithms are shown to correctly reconstruct and represent the staggered acquired image on a standard display.